Nothing Special   »   [go: up one dir, main page]

CN118213279A - Rf半导体装置及其制造方法 - Google Patents

Rf半导体装置及其制造方法 Download PDF

Info

Publication number
CN118213279A
CN118213279A CN202410309435.8A CN202410309435A CN118213279A CN 118213279 A CN118213279 A CN 118213279A CN 202410309435 A CN202410309435 A CN 202410309435A CN 118213279 A CN118213279 A CN 118213279A
Authority
CN
China
Prior art keywords
molding compound
layer
silicon
active layer
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202410309435.8A
Other languages
English (en)
Inventor
朱利奥·C·科斯塔
迈克尔·卡罗尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qorvo US Inc
Original Assignee
Qorvo US Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qorvo US Inc filed Critical Qorvo US Inc
Publication of CN118213279A publication Critical patent/CN118213279A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737—Organic materials with or without a thermoconductive filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

本公开涉及RF半导体装置及其制造方法。本公开涉及一种射频装置，其包含：具有后段工艺部分和前段工艺部分的装置区、第一凸块结构、第一模制化合物，以及第二模制化合物。所述FEOL部分包含有源层、接触层和隔离区段。所述有源层和所述隔离区段位于所述接触层上方，且所述有源层由所述隔离区段围绕。所述BEOL部分形成于所述FEOL部分下方，且所述第一凸块结构和所述第一模制化合物形成于所述BEOL部分下方。每个第一凸块结构由所述第一模制化合物部分地囊封，且经由所述BEOL部分内的连接层电耦合到所述FEOL部分。所述第二模制化合物位于所述有源层上方而无硅材料，其电阻率介于5欧姆‑厘米与30000欧姆‑厘米之间。

Description

RF半导体装置及其制造方法
本申请是国际申请日为2019年5月30日、国际申请号为PCT/US2019/034645、进入中国国家阶段日为2021年1月28日、申请号为201980050433.9、发明创造名称为“RF半导体装置及其制造方法”的发明申请的分案申请。
相关申请案
本申请要求于2018年7月2日提交的第62/692,945号临时专利申请的权益，所述临时专利申请的公开内容特此以全文引用的方式并入本文中。
本申请关于标题为“具有增强性能的RF装置及其形成方法(RF DEVICES WITHENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME)”的同时提交的第号美国专利申请，所述美国专利申请的公开内容特此以全文引用的方式并入本文中。
技术领域
本公开涉及一种射频(RF)装置及其制造方法，且更确切地说，涉及具有增强的热和电性能的RF装置以及用以提供具有增强的性能的RF装置的晶片级封装工艺。
背景技术
蜂窝式及无线装置的广泛利用驱动射频(RF)技术的快速发展。在其上制造RF装置的衬底在实现RF技术的高水平性能方面起着重要作用。在常规硅处置衬底上制造RF装置可能会受益于硅材料的低成本、大规模的晶片生产能力、完善的半导体设计工具以及完善的半导体制造技术。
尽管将常规硅处置衬底用于RF装置制造具有益处，但在工业中众所周知，常规硅处置衬底对于RF装置可能具有两个不合需要的特性：谐波失真和低电阻率值。谐波失真是在硅处置衬底上构建的RF装置中实现高水平线性度的关键障碍。此外，高速且高性能的晶体管更紧密地集成在RF装置中。因此，由于集成在RF装置中的大量晶体管、通过晶体管的大量电力和/或晶体管的高操作速度，RF装置生成的热量将显著增大。因此，需要以实现更好散热的配置来封装RF装置。
为了适应RF装置的增大的热生成且减小RF装置的有害谐波失真，因此，本公开的目的是提供一种改进的封装工艺以增强热和电性能。另外，还需要在不增大封装大小的情况下增强RF装置的性能。
发明内容
本公开涉及一种具有增强的热和电性能的射频(RF)装置及其制造方法。所公开的RF装置包含装置区、数个第一凸块结构、第一模制化合物和第二模制化合物。所述装置区包含具有数个连接层的后段工艺(BEOL)部分和位于所述BEOL部分上方的前段工艺(FEOL)部分。所述FEOL部分包含有源层、接触层和隔离区段。本文中，所述有源层和所述隔离区段两者皆位于所述接触层上方。所述有源层由所述隔离区段围绕，且不在竖直上延伸超出所述隔离区段。所述第一凸块结构形成于所述BEOL部分的底表面处，且经由所述BEOL部分内的所述连接层电耦合到所述FEOL部分。所述第一模制化合物形成于所述BEOL部分的所述底表面上，且部分地囊封每个第一凸块结构，使得每个第一凸块结构的底部部分不由所述第一模制化合物覆盖。所述第二模制化合物位于所述FEOL部分的所述有源层上方而无硅材料，其电阻率介于5欧姆-厘米与30000欧姆-厘米之间。
在所述RF装置的一个实施例中，所述第二模制化合物的一部分位于所述隔离区段上方。
在所述RF装置的一个实施例中，所述隔离区段在竖直上延伸超出所述有源层的顶表面，以在所述隔离区段内且在所述有源层上方界定开口，其中所述第二模制化合物填充所述开口。
根据另一个实施例，所述RF装置进一步包含直接在所述有源层的所述顶表面上方且在所述开口内的钝化层。本文中，所述钝化层由二氧化硅、氮化硅或两者的组合形成，且与所述第二模制化合物接触。
根据另一实施例，所述RF装置进一步包含直接在所述有源层的所述顶表面上方且在所述开口内的界面层。本文中，所述界面层由硅锗(SiGe)形成，且直接连接到第二模具。
在所述RF装置的一个实施例中，所述第二模制化合物与所述有源层的所述顶表面接触。
在所述RF装置的一个实施例中，每个隔离区段的顶表面与所述有源层的顶表面是共面的。本文中，所述第二模制化合物位于所述有源层和所述隔离区段两者上方。
根据另一实施例，所述RF装置进一步包含数个第二凸块结构。每个第二凸块结构与对应的第一凸块结构接触，且从所述第一模制化合物突出。
在所述RF装置的一个实施例中，所述第二凸块结构由焊膏、导电环氧树脂或可回流金属形成。
在所述RF装置的一个实施例中，所述第一凸块结构是焊球或铜柱。
在所述RF装置的一个实施例中，所述第一模制化合物由与所述第二模制化合物相同的材料形成。本文中，所述第一模制化合物和所述第二模制化合物的热导率大于1W/m·K，且介电常数小于8或介电常数在3与5之间。
在所述RF装置的一个实施例中，所述第一模制化合物与所述第二模制化合物由不同的材料形成。
在所述RF装置的一个实施例中，所述第一模制化合物是透明的。
在所述RF装置的一个实施例中，所述FEOL部分经配置以提供开关场效应晶体管(FET)、二极管、电容器、电阻器和电感器中的至少一个。
根据示例性过程，首先提供具有数个装置裸片的装置晶片。本文中，每个装置裸片包含第一凸块结构和装置区，所述装置区具有BEOL部分和在所述BEOL部分上方的FEOL部分。所述FEOL部分包含有源层、接触层和隔离区段。本文中，所述有源层和所述隔离区段位于所述接触层上方，所述隔离区段围绕所述有源层，且所述有源层不在竖直上延伸超出所述隔离区段。每个BEOL部分的底表面的组合形成所述装置晶片的底表面。所述第一凸块结构形成于每个BEOL部分的所述底表面处。此外，由SiGe形成的界面层直接在每个装置裸片的所述有源层上方。硅处置衬底直接在每个界面层的上方。接下来，将第一模制化合物涂覆在所述装置晶片的所述底表面上方以囊封每个装置裸片的所述第一凸块结构。接着完全移除所述硅处置衬底。在移除了所述硅处置衬底的每个装置裸片的所述有源层上方形成第二模制化合物。在所述第二模制化合物与每个有源层之间不存在硅材料。在形成所述第二模制化合物之后，将所述第一模制化合物减薄，直到暴露每个第一凸块结构的底部部分。
根据另一实施例，所述示例性过程进一步包含在涂覆所述第二模制化合物之前移除所述界面层。本文中，在涂覆所述第二模制化合物之后，每个装置裸片的所述有源层与所述第二模制化合物接触。
根据另一实施例，所述示例性过程进一步包含在涂覆所述第二模制化合物之前，移除所述界面层且直接在每个装置裸片的所述有源层上方施加钝化层。本文中，所述钝化层由二氧化硅、氮化硅或两者的组合形成。在涂覆所述第二模制化合物之后，所述钝化层与所述第二模制化合物接触。
根据另一实施例，所述示例性过程进一步包含在使所述第一模制化合物减薄之后形成数个第二凸块结构。本文中，每个第二凸块结构与对应的第一凸块结构的暴露底部部分接触，且从所述第一模制化合物突出。
根据另一实施例，所述示例性过程进一步包含在涂覆所述第一模制化合物之前，在所述装置晶片的所述底表面的外围处形成至少一个窗口组件。本文中，在涂覆所述第一模制化合物之后，所述至少一个窗口组件由所述第一模制化合物囊封。
在所述示例性过程的一个实施例中，所述至少一个窗口组件比每个第一凸块结构高，使得在所述减薄过程期间，所述至少一个窗口组件在所述第一凸块结构之前暴露。
在所述示例性过程的一个实施例中，提供所述装置晶片开始于提供Si-SiGe-Si晶片，所述Si-SiGe-Si晶片包含公共硅外延层、在所述公共硅外延层上方的公共界面层以及在所述公共界面层上方的所述硅处置衬底。所述公共界面层由SiGe形成。接着执行互补金属氧化物半导体(CMOS)过程以提供包含数个装置区的前体晶片。本文中，所述隔离区段延伸穿过所述公共硅外延层和所述公共界面层且延伸到所述硅处置衬底中，使得所述公共界面层分离为数个个别界面层，且所述公共硅外延层分离成数个个别硅外延层。所述装置区的每个有源层由对应的个别硅外延层形成。每个个别界面层直接位于对应有源层的顶表面上方，且所述硅处置衬底直接位于所述个别界面层上方。接下来，在每个BEOL部分的所述底表面处形成所述第一凸块结构，以从所述装置区完成所述装置裸片。
在所述示例性过程的一个实施例中，提供所述装置晶片开始于提供Si-SiGe-Si晶片，所述Si-SiGe-Si晶片包含公共硅外延层、在所述公共硅外延层上方的公共界面层以及在所述公共界面层上方的所述硅处置衬底。所述公共界面层包含SiGe，且具有连接的数个界面层。接着执行CMOS过程以提供包含数个装置区的前体晶片。本文中，所述隔离区段延伸穿过所述公共硅外延层且延伸到所述公共界面层中，使得所述公共硅外延层分离成数个个别硅外延层，且所述界面层保持连接。所述装置区的每个有源层由对应的个别硅外延层形成。每个界面层直接位于对应有源层的顶表面上方，且所述硅处置衬底保持直接位于所述公共界面层上方。接下来，在每个BEOL部分的所述底表面处形成所述第一凸块结构，以从所述装置区完成所述装置裸片。
本领域的技术人员在结合附图阅读优选实施例的以下详细描述之后，将了解本公开的范围且认识到本公开的额外方面。
附图说明
并入在本说明书中并且形成本说明书的一部分的附图说明本公开的若干方面，且与描述一起用以解释本公开的原理。
图1展示根据本公开的一个实施例的具有增强的热和电性能的示例性射频(RF)装置。
图2至图13提供示例性晶片级封装工艺，其说明制造图1所示的示例性RF装置的步骤。
应理解，为了清楚地说明，图1至图13可能未按比例绘制。
具体实施方式
下文阐述的实施例表示使本领域的技术人员能够实践实施例的必要信息，且说明实践实施例的最佳模式。在根据附图阅读以下描述后，本领域的技术人员将理解本公开的概念且将认识到本文中并未特定阐释的这些概念的应用。应理解，这些概念和应用落入本公开和所附权利要求书的范围内。
应理解，虽然术语第一、第二等可在本文中用以描述各种元件，但这些元件不应受这些术语限制。这些术语仅用于区分一个元件与另一元件。举例来说，在不脱离本公开的范围的情况下，第一元件可称为第二元件，且类似地，第二元件可称为第一元件。如本文中所使用，术语“和/或”包含相关联所列项目中的一或多者的任何和所有组合。
将理解，当例如层、区或衬底的元件被称为在另一元件“上”或延伸“到”另一元件“上”时，其可以直接在所述另一元件上或直接延伸到另一元件上，或也可能存在介入元件。相比之下，当元件被称为“直接在”另一元件“上”或“直接”延伸“到”另一元件“上”时，不存在介入元件。同样，应理解，当例如层、区或衬底的元件被称为在另一元件“上方”或在其“上方”延伸时，其可直接在另一元件上方或在另一元件上方延伸，或也可存在介入元件。相比之下，当元件被称为“直接在”另一元件“上方”或“直接”在另一元件“上方”延伸时，不存在介入元件。还应理解，当元件被称为“连接”或“耦合”到另一元件时，其可直接连接或耦合到另一元件，或可存在介入元件。相比之下，当元件被称作“直接连接”或“直接耦合”到另一元件时，不存在插入元件。
在本文中可使用例如“下方”或“上方”或“上部”或“下部”或“水平”或“垂直”的相对术语来描述一个元件、层或区与另一元件、层或区的关系，如图所示。应理解，这些术语和上文所论述的术语既定涵盖除图式中所描绘的定向以外的装置的不同定向。
本文中所使用的术语仅出于描述特定实施例的目的，且并非意在限制本公开。如本文中所使用，除非上下文另外明确指示，否则单数形式“一”和“所述”既定还包含复数形式。应进一步理解，术语“包括(comprises、comprising)”、“包含(includes及/或including)”在本文中使用时指定所陈述的特征、整数、步骤、操作、元件及/或组件的存在，但并不排除一或多个其它特征、整数、步骤、操作、元件、组件及/或其群组的存在或添加。
除非另外定义，否则本文中所使用的所有术语(包含技术和科学术语)具有与本公开所属领域的普通技术人员通常所理解的相同的意义。将进一步理解，本文中所使用的术语应解释为在本说明书及相关技术的上下文中具有与其含义一致的含义且将不在理想化或过度正式意义上进行解释，除非本文中明确地如此定义。
预计在未来几年内常规射频绝缘体上硅(RFSOI)晶片会逐渐出现短缺，正在设计替代技术，以解决对使用硅晶片的高电阻率、富阱层形成和智能切割SOI晶片过程的需要。这些替代技术中的一个是基于使用硅锗(SiGe)界面层代替硅衬底与硅外延层之间的内埋氧化物层(BOX)，然而，这些替代技术也会由于硅衬底而遭受有害的失真效应，类似于RFSOI技术中观察到的失真效应。本公开涉及具有增强的热性能和电性能的射频(RF)装置及用于制造其的晶片级封装工艺，其基于此Si-SiGe-Si结构，而没有来自硅衬底的有害失真效应。
图1展示根据本公开的一个实施例的由Si-SiGe-Si晶片形成的示例性RF装置10(在以下段落中描述处理细节)。出于此说明的目的，示例性RF装置10包含装置区12、第一凸块结构14、第一模制化合物16和第二模制化合物18。
详细地说，装置区12包含前段工艺(FEOL)部分20和在FEOL部分20下方的后段工艺(BEOL)部分22。在一个实施例中，FEOL部分20经配置以提供开关场效应晶体管(FET)，且包含有源层24和接触层26。本文中，有源层24具有源极28、漏极30以及在源极28与漏极30之间的通道32。源极28、漏极30和通道32由相同的硅外延层形成。接触层26形成于有源层24的下方，且包含栅极结构34、源极触点36、漏极触电38和栅极触电40。栅极结构34可由氧化硅形成，且在通道32下方水平(从源极28下方到漏极30下方)延伸。源极触点36连接到源极28且在其下方，漏极触点38连接到漏极30且在其下方，且栅极触点40连接到栅极结构34且在其下方。绝缘材料42可形成于源极触点36、漏极触点38、栅极结构34和栅极触点40周围以电分离源极28、漏极30和栅极结构34。在不同应用中，FEOL部分20可具有不同的FET配置或提供不同的装置组件，例如二极管、电容器、电阻器和/或电感器。
此外，FEOL部分20还包含隔离区段44，其位于接触层26的绝缘材料42上方且围绕有源层24。隔离区段44经配置以将RF装置10，特别是将有源层24与形成于公共晶片(未展示)中的其它装置电分离。本文中，隔离区段44可从接触层26的顶表面延伸，且在竖直上延伸超出有源层24的顶表面，以界定在隔离区段44内且在有源层24上方的开口46。第二模制化合物18填充开口46，且可在隔离区段44上方延伸。隔离区段44可由二氧化硅形成，二氧化硅可抵抗例如氢氧化钾(KOH)、氢氧化钠(NaOH)和乙酰胆碱(ACH)的蚀刻化学物质。
在一些应用中，RF装置10可进一步包含直接在有源层24的顶表面上方且在开口46内的钝化层48，其由二氧化硅、氮化硅或两者的组合形成。由此，第二模制化合物18直接在钝化层48上方。钝化层48经配置以终止有源层24的表面结合，这可能导致不希望的泄漏。钝化层还可充当屏障，且经配置以保护有源层24免受湿气或离子污染。如果省略钝化层48，则第二模制化合物18可能会与有源层24的顶表面接触。在一些应用中，RF装置10可进一步包含界面层(在以下段落中描述且未在本文中展示)，其由SiGe直接形成于有源层24的顶表面上方和开口46内。由此，第二模制化合物18可直接在界面层上方。界面层来自用于制造RF装置10的Si-SiGe-Si晶片(在以下段落中描述处理细节)。如果省略界面层，则第二模制化合物18可能会与有源层24的顶表面接触。注意，无关于钝化层48或界面层，在第二模制化合物18与有源层24的顶表面之间不存在没有锗含量的硅晶体。钝化层48和界面层两者皆为硅合金。
另外，在一些应用中，每个隔离区段44的顶表面与有源层24的顶表面是共面的(未展示)，且省略了开口46。第二模制化合物18位于有源层24和FEOL部分20的隔离区段44两者上方。注意，有源层24从不在竖直上超出隔离区段44。
BEOL部分22在FEOL部分20下方，且包含形成于介电层52内的多个连接层50。第一凸块结构14形成于BEOL部分22的底表面上，且经由BEOL部分22的连接层50电耦合到FEOL部分20(在此图示中为源极触点36和漏极触点38)。第一模制化合物16形成于BEOL部分22下方，且囊封每个第一凸块结构14的各侧，使得每个第一凸块结构14的底部部分不由第一模制化合物16覆盖。
本文中，第一凸块结构14不从第一模制化合物16的底表面突出。在一些应用中，希望在RF装置10的底表面具有突出结构，以促进且改进裸片附接(到印刷电路板)操作的可靠性。因此，RF装置10可进一步包含数个第二凸块结构54。每个第二凸块结构54与对应的第一凸块结构14接触，且从第一模制化合物16的底表面突出。第一凸块结构14可为焊球或铜柱。第二凸块结构54可由焊膏、导电环氧树脂或可回流金属形成。
在装置区12中生成的热可向上行进到第二模制化合物18的在有源层24上方的底部部分，且接着将向下穿过装置区12和第一凸块结构14，其将耗散所述热。另外，在装置区12中生成的热也可直接行进通过第一模制化合物16进行传导。因此，非常希望第一模制化合物16和第二模制化合物18两者皆具有高热导率。第一模制化合物16和第二模制化合物18可具有大于1W/m·K或大于10W/m·K的热导率。此外，第一模制化合物16和第二模制化合物18可具有小于8或在3与5之间的低介电常数以产生低RF耦合。第一模制化合物16可由与第二模制化合物18相同或不同的材料形成。在一个实施例中，第一模制化合物16和第二模制化合物18两者皆可由热塑性塑料或热固性聚合物材料(例如PPS(聚苯硫醚)，掺杂有氮化硼、氧化铝、碳纳米管或类金刚石热添加剂的包覆模制环氧树脂等)形成。另外，第一模制化合物16可为透明的，且可具有在25μm与500μm之间的厚度(基于第一凸块结构14的大小)。第二模制化合物18的厚度是基于RF装置10的所需热性能、装置布局、与第一凸块结构14的距离以及封装和组装的细节。第二模制化合物18可具有在200μm与500μm之间的厚度。
图2至图13提供示例性晶片级封装工艺，其说明制造图1所示的示例性RF装置10的步骤。尽管示例性步骤说明为系列，但示例性步骤不一定取决于次序。一些步骤可能以与所呈现的次序不同的次序进行。另外，本公开的范围内的过程可包含比图2至图13中说明的过程更少或更多的步骤。
首先，如图2如中所说明，提供Si-SiGe-Si晶片56。Si-SiGe-Si晶片56包含公共硅外延层58、在公共硅外延层58上方的公共界面层60，和在公共界面层60上方的硅处置衬底62。本文中，由SiGe形成的公共界面层60将公共硅外延层58与硅处置衬底62分离。
本文中，公共硅外延层58由具有所需硅外延特性以形成电子装置的装置级硅材料形成。公共界面层60由具有任何摩尔比的Si和Ge的合金形成。Ge浓度越高，硅处置衬底62与公共界面层60之间的蚀刻选择性越好，但公共硅外延层58的外延生长也变得越困难。在一个实施例中，公共界面层60可具有大于15％或大于25％的Ge浓度。Ge浓度在整个公共界面层60中可为均一的。在一些应用中，Ge浓度可在竖直上递变(在1％与50％之间)，以便为公共硅外延层58的生长产生必要的应变消除。硅处置衬底62可由常规的低成本、低电阻率和高介电常数硅组成。公共硅外延层58的电阻率高于硅处置衬底62，且公共硅外延层58的谐波生成率低于硅处置衬底62。公共硅外延层58的厚度可在700nm与2000nm之间，公共界面层60的厚度可在100nm与1000nm之间，且硅处置衬底62的厚度可在200μm与500μm之间。
接下来，如图3A中所说明，对Si-SiGe-Si晶片56执行互补金属氧化物半导体(CMOS)处理，以提供具有数个装置区12的前体晶片64。出于此说明的目的，每个装置区12的FEOL部分20经配置以提供开关FET。在不同应用中，FEOL部分20可具有不同的FET配置或提供不同的装置组件，例如二极管、电容器、电阻器和/或电感器。
在此实施例中，每个装置区12的隔离区段44延伸穿过公共硅外延层58和公共界面层60，且延伸到硅处置衬底62中。由此，公共界面层60分离成数个个别界面层60I，且公共硅外延层58分离成数个个别硅外延层58I，其中的每一个用于在一个装置区12中形成对应有源层24。
有源层24的顶表面与对应的界面层60I接触。硅处置衬底62位于每个个别界面层60I上方，且硅处置衬底62的部分可位于隔离区段44上方。装置区12的至少包含多个连接层50和介电层52的BEOL部分22形成于FEOL部分20下方。某些连接层50的底部部分经由介电层52暴露于BEOL部分22的底表面处。
在另一实施例中，隔离区段44不延伸到硅处置衬底62中。相反，隔离区段44仅延伸穿过公共硅外延层58且延伸到公共界面层60中，如图3B中所说明。本文中，公共界面层60保持连续，且个别界面层60I彼此连接。公共界面层60直接位于每个有源层24的顶表面上方，且直接位于每个隔离区段44的顶表面上方。硅处置衬底62保持在公共界面层60上方。另外，隔离区段44可延伸穿过公共硅外延层58，但不延伸到公共界面层60中。每个隔离区段44的顶表面和每个有源层24的顶表面可为共面的(未展示)。公共界面层60在每个隔离区段44和每个有源层24上方，且硅处置衬底62保持在公共界面层60上方。
接着，在每个BEOL部分22的底表面处形成第一凸块结构14，以提供装置晶片66，如图4中所描绘。每个BEOL部分22的底表面的组合形成装置晶片66的底表面。装置晶片66包含数个装置裸片68，与装置区12相比，每个装置裸片进一步包含第一凸块结构14。每个第一凸块结构14与对应连接层50的暴露部分接触。本文中，第一凸块结构14经由BEOL部分22的连接层50电耦合到FEOL部分20(在此说明中为源极触点36和漏极触点38)。第一凸块结构14可通过焊球凸起技术或铜柱封装技术形成。每个第一凸块结构14从BEOL部分22的底表面突出20μm与350μm之间。
接下来，如图5中所说明，可在一个BEOL部分22的一个或多个晶片标记(未展示)所位于的底表面处形成至少一个窗口组件70。本文中，晶片标记指示晶片的关键位置，将在随后的单分和/或组装过程中将其用于对准。在一个实施例中，至少一个窗口组件70位于装置晶片66的底表面的外围。至少一个窗口组件70可由透明材料(例如：透明聚硅氧材料)形成，使得可经由至少一个窗口组件70看到晶片标记。此外，至少一个窗口组件70可由易于移除的材料(例如：丙烯酸聚合物)形成，使得在容易地移除至少一个窗口组件70(更多详情见以下论述)之后将看到晶片标记。至少一个窗口组件70具有大于每个第一凸块结构14的高度的高度，且不连接到任何第一凸块结构14。注意，至少一个窗口组件70是可选的。在一些应用中，可省略在一个BEOL部分22的底表面处形成至少一个窗口组件70。
第一模制化合物16涂覆在装置晶片66的底表面上方，且囊封每个第一凸块结构14和至少一个窗口组件70，如图6中所说明。第一模制化合物16可通过各种程序涂覆，例如压缩模制、片材模制、包覆模制、传递模制、围坝填充囊封或丝网印刷囊封。第一模制化合物16可具有大于1W/m·K或大于10W/m·K的优良热导率，且可具有小于8或在3与5之间的介电常数。第一模制化合物16可具有在25μm与500μm之间的厚度。第一模制化合物16可抵抗例如KOH、NaOH和ACH的蚀刻化学物质。在一些应用中，第一模制化合物16可由透明材料形成。由此，由于可经由第一模制化合物16看到晶片的所有位置，因此不需要在BEOL部分22的底表面处形成至少一个窗口组件70。接着使用固化处理(未展示)来硬化第一模制化合物16。固化温度介于100℃与320℃之间，具体取决于哪种材料用作第一模制化合物16。
在形成第一模制化合物16之后，选择性地移除硅处置衬底62以提供经蚀刻晶片72，其中在每个界面层60I上停止选择性移除，如图7中所说明。如果隔离区段44在竖直上延伸超出界面层60I，则移除硅处置衬底62将在每个有源层24上方和隔离区段44内提供开口46。移除硅处置衬底62可通过化学机械研磨和利用湿式/干式蚀刻剂化学物质(其可为TMAH、KOH、NaOH、ACH或XeF2)的蚀刻过程来提供，或通过蚀刻过程本身提供。作为实例，可将硅处置衬底62研磨到较薄的厚度以减少随后的蚀刻时间。接着执行蚀刻过程以完全移除剩余的硅处置衬底62。由于硅处置衬底62与界面层60I具有不同的特性，所以其对于相同的蚀刻技术可能具有不同反应(例如：对于相同蚀刻剂的不同蚀刻速度)。因此，蚀刻系统能够识别界面层60I的存在，且能够指示何时停止蚀刻过程。
在移除过程期间，不移除隔离区段44，且因此保护每个FEOL部分20。第一模制化合物16保护每个BEOL部分22的底表面。本文中，在移除过程之后，暴露每个隔离区段44的顶表面和每个界面层60I的顶表面。如果隔离区段44延伸到公共界面层60中(如图3B所示)，或每个隔离区段44的顶表面与每个有源层24的顶表面是共面的(未展示)，则仅公共界面层60的顶表面将暴露(未展示)。
由于SiGe材料的窄间隙性质，界面层60I(或公共界面层60)可能导电。界面层60I可能在有源层24的源极28与漏极30之间引起明显的泄漏。因此，在例如FET应用的一些应用中，希望也移除界面层60I(或公共界面层60)，如图8中所说明。界面层60I可通过与用于移除硅处置衬底62的蚀刻过程相同的蚀刻过程来移除，或可通过例如HCI干式蚀刻系统的另一蚀刻过程移除。如果界面层60I足够薄，则其可能完全耗尽，且可能不会在FEOL部分20的源极28与漏极30之间引起任何明显的泄漏。在此情况下，界面层60I可保持不变。
在一些应用中，可由二氧化硅、氮化硅或两者的组合形成的钝化层48可直接形成于每个FEOL部分20的有源层24上方，如图9中所说明。如果在每个有源层24上方且在隔离区段44内存在一个开口46，则钝化层48在开口46内。钝化层48经配置以终止有源层24的顶表面处的表面结合，这可能导致不希望的泄漏。钝化层48可通过CVD介电膜或钝化等离子体形成。
接着，将第二模制化合物18涂覆于经蚀刻晶片72上方，如图10中所说明。本文中，第二模制化合物18填充每个开口46，且与开口46内的钝化层48接触。此外，第二模制化合物18的部分可在隔离区段44上方延伸。如果在每个开口46中并未形成钝化层48，则第二模制化合物18与每个有源层24的顶表面(未展示)接触。如果界面层60I保持在每个有源层24的顶表面上方，则第二模制化合物18与界面层60I(未展示)接触。第二模制化合物18始终在每个有源层24上方。
第二模制化合物18可通过各种程序涂覆，例如压缩模制、片材模制、包覆模制、传递模制、围坝填充囊封或丝网印刷囊封。在第二模制化合物18的模制过程期间，第一模制化合物16为经蚀刻晶片72提供机械强度和刚度。随后进行固化处理(未展示)以硬化第二模制化合物18。固化温度介于100℃与320℃之间，具体取决于哪种材料用作第二模制化合物18。在固化处理之后，可使第二模制化合物18减薄和/或平坦化(未展示)。
接下来，减薄第一模制化合物16以提供模制装置晶片74，如图11中所说明。本文中，第一模制化合物囊封每个第一凸块结构14的侧面，且每个第一凸块结构14的底部部分暴露。此外，由于至少一个窗口组件70的高度大于每个第一凸块结构14的高度，因此至少一个窗口组件70的底部部分也经由第一模制化合物16暴露。减薄程序可利用机械研磨工艺进行。在一个实施例中，至少一个窗口组件70可由透明材料形成，使得指示晶片的关键位置的晶片标记将经由至少一个窗口组件70被看到。在另一实施例中，至少一个窗口组件70可由不透明材料形成，使得指示晶片的关键位置的晶片标记将不会经由至少一个窗口组件70被看到。需要移除至少一个窗口组件70的额外步骤来暴露指示晶片的关键位置(未展示)的晶片标记。
另外，在一些应用中，第二凸块结构54可在第一模制化合物16减薄之后形成，如图12中所说明。每个第二凸块结构54直接连接到对应的第一凸块结构14、电耦合到对应的FEOL部分20，且从第一模制化合物16的底表面突出。最后，将模制装置晶片74单分成个别RF装置10，如图13中所说明。单分步骤可通过在特定隔离区段44处的探测和切割过程来提供。个别RF装置10可使用数个裸片附接方法组装在PCB上。
所属领域的技术人员将认识到对本公开的优选实施例的改进和修改。所有此类改进和修改被视为在本文中公开的概念和所附的权利要求书的范围内。

Claims (19)

1.一种方法，包括
·形成具有多个装置裸片的装置晶片，所述多个装置裸片中的每一个包括有源层；
·将第一模制化合物涂敷于所述装置晶片的底表面上方，以囊封所述装置晶片的所述多个装置裸片中的每一个的多个第一凸块结构；
·从所述装置晶片完全移除硅处置衬底以提供蚀刻晶片，其中
·所述硅处置衬底直接位于多个界面层中的每一个上方，所述多个界面层中的每一个分别直接位于所述多个装置裸片中的对应的一个装置裸片的有源层上方；以及
·所述多个界面层中的每一个由硅锗SiGe形成；
·将第二模制化合物涂覆于移除了硅处置衬底的所述多个装置裸片中的每一个的有源层上方，其中，没有硅材料位于第二模制化合物和每个有源层之间；以及
·将所述第一模制化合物减薄，直到暴露所述多个第一凸块结构中的每一个的底部部分。
2.根据权利要求1所述的方法，还包括在涂覆第二模制化合物之前移除所述多个界面层中的每一个。
3.根据权利要求2所述的方法，其中所述多个装置裸片中的每一个的所述有源层在涂覆所述第二模制化合物之后与所述第二模制化合物接触。
4.根据权利要求2所述的方法，还包括在移除所述多个界面层中的每一个之后且在涂覆第二模制化合物之前，直接在所述多个装置裸片中的每一个的所述有源层上方施加钝化层，其中：
·所述钝化层由二氧化硅、氮化硅或两者的组合形成；且
·在涂覆所述第二模制化合物之后，所述钝化层与所述第二模制化合物接触。
5.根据权利要求1所述的方法，进一步包括在将所述第一模制化合物减薄之后形成多个第二凸块结构，其中所述多个第二凸块结构中的每一个与对应的第一凸块结构的暴露的底部部分接触，且从所述第一模制化合物突出。
6.根据权利要求5所述的方法，其中所述多个第二凸块结构由焊膏、导电环氧树脂或可回流金属形成。
7.根据权利要求1所述的方法，进一步包括在涂覆所述第一模制化合物之前，在所述装置晶片的所述底表面的外围处形成至少一个窗口组件，其中在涂覆所述第一模制化合物之后，所述至少一个窗口组件由所述第一模制化合物囊封。
8.根据权利要求7所述的方法，其中所述至少一个窗口组件比所述多个第一凸块结构中的每一个高，使得在减薄过程期间，所述至少一个窗口组件在所述多个第一凸块结构之前暴露。
9.根据权利要求1所述的方法，其中
·所述多个装置裸片中的每一个包含多个第一凸块结构和装置区，所述装置区具有后段工艺BEOL部分和在所述BEOL部分上方的前段工艺FEOL部分；
·所述FEOL部分包括有源层、接触层和隔离区段，其中所述有源层和所述隔离区段位于所述接触层上方，所述隔离区段围绕所述有源层，且所述有源层不在竖直上延伸超出所述隔离区段；
·所述多个第一凸块结构形成于所述多个装置裸片中的每一个的所述BEOL部分的底表面处，其中每个BEOL部分的所述底表面的组合形成所述装置晶片的底表面。
10.根据权利要求9所述的方法，其中所述FEOL部分经配置以提供开关场效应晶体管FET、二极管、电容器、电阻器和电感器中的至少一个。
11.根据权利要求9所述的方法，其中形成装置晶片包括：
·提供Si-SiGe-Si晶片，所述Si-SiGe-Si晶片包含公共硅外延层、在所述公共硅外延层上方的公共界面层以及在所述公共界面层上方的所述硅处置衬底，其中所述公共界面层由SiGe形成；
·执行互补金属氧化物半导体CMOS过程以提供包含多个装置区的前体晶片，其中：
·所述隔离区段延伸穿过所述公共硅外延层和所述公共界面层且延伸到所述硅处置衬底中，使得所述公共界面层单独地分离为多个界面层，且所述公共硅外延层分离成多个个别硅外延层，其中：
·所述多个装置区的每个有源层由对应的个别硅外延层形成；且
·所述多个界面层中的每一个直接位于对应有源层的顶表面上方，且所述硅处置衬底直接位于所述多个界面层上方；以及
·在每个BEOL部分的所述底表面处形成所述多个第一凸块结构，以从所述多个装置区完成所述多个装置裸片。
12.根据权利要求9所述的方法，其中形成所述装置晶片包括：
·提供Si-SiGe-Si晶片，所述Si-SiGe-Si晶片包含公共硅外延层、在所述公共硅外延层上方的公共界面层以及在所述公共界面层上方的所述硅处置衬底，其中：
·所述公共界面层包括SiGe；且
·所述公共界面层具有彼此连接的多个界面层；
·执行CMOS过程以提供包含多个装置区的前体晶片，其中：
·所述隔离区段延伸穿过所述公共硅外延层且延伸到所述公共界面层中，
使得所述公共硅外延层分离成多个个别硅外延层，且所述多个界面层保持彼此连接；
·所述多个装置区的每个有源层由对应的个别硅外延层形成；且
·所述多个界面层中的每一个直接位于对应有源层的顶表面上方，且所述硅处置衬底保持直接位于所述公共界面层上方；以及
·在每个BEOL部分的所述底表面处形成所述多个第一凸块结构，以从所述多个装置区完成所述多个装置裸片。
13.根据权利要求1所述的方法，其中所述多个第一凸块结构是焊球或铜柱。
14.根据权利要求1所述的方法，其中所述第一模制化合物由与所述第二模制化合物相同的材料形成。
15.根据权利要求14所述的方法，其中所述第一模制化合物和所述第二模制化合物的热导率大于1W/m·K。
16.根据权利要求14的方法，其中所述第一模制化合物和所述第二模制化合物的介电常数小于8。
17.根据权利要求14所述的方法，其中所述第一模制化合物和所述第二模制化合物的介电常数在3与5之间。
18.根据权利要求1所述的方法，其中所述第一模制化合物与所述第二模制化合物由不同的材料形成。
19.根据权利要求1所述的方法，其中所述第一模制化合物是透明的。
CN202410309435.8A 2018-07-02 2019-05-30 Rf半导体装置及其制造方法 Pending CN118213279A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862692945P 2018-07-02 2018-07-02
US62/692,945 2018-07-02
PCT/US2019/034645 WO2020009759A1 (en) 2018-07-02 2019-05-30 Rf semiconductor device and manufacturing method thereof
CN201980050433.9A CN112534553B (zh) 2018-07-02 2019-05-30 Rf半导体装置及其制造方法

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201980050433.9A Division CN112534553B (zh) 2018-07-02 2019-05-30 Rf半导体装置及其制造方法

Publications (1)

Publication Number Publication Date
CN118213279A true CN118213279A (zh) 2024-06-18

Family

ID=66999908

Family Applications (2)

Application Number Title Priority Date Filing Date
CN202410309435.8A Pending CN118213279A (zh) 2018-07-02 2019-05-30 Rf半导体装置及其制造方法
CN201980050433.9A Active CN112534553B (zh) 2018-07-02 2019-05-30 Rf半导体装置及其制造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201980050433.9A Active CN112534553B (zh) 2018-07-02 2019-05-30 Rf半导体装置及其制造方法

Country Status (5)

Country Link
US (2) US20200006193A1 (zh)
EP (1) EP3818558A1 (zh)
CN (2) CN118213279A (zh)
TW (1) TWI848952B (zh)
WO (1) WO2020009759A1 (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12062700B2 (en) 2018-04-04 2024-08-13 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
CN118213279A (zh) 2018-07-02 2024-06-18 Qorvo美国公司 Rf半导体装置及其制造方法
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US12046570B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12125825B2 (en) 2019-01-23 2024-10-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12057374B2 (en) 2019-01-23 2024-08-06 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
WO2020153983A1 (en) 2019-01-23 2020-07-30 Qorvo Us, Inc. Rf semiconductor device and manufacturing method thereof
US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US12129168B2 (en) 2019-12-23 2024-10-29 Qorvo Us, Inc. Microelectronics package with vertically stacked MEMS device and controller device
WO2022186857A1 (en) * 2021-03-05 2022-09-09 Qorvo Us, Inc. Selective etching process for si-ge and doped epitaxial silicon

Family Cites Families (377)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS505733Y1 (zh) 1970-02-23 1975-02-18
JPS6013257B2 (ja) 1976-02-20 1985-04-05 松下電器産業株式会社 二次電子増倍体およびその製造方法
JPS5338954A (en) 1976-09-21 1978-04-10 Mitsubishi Electric Corp Strip line circulator
US4366202A (en) 1981-06-19 1982-12-28 Kimberly-Clark Corporation Ceramic/organic web
US5061663A (en) 1986-09-04 1991-10-29 E. I. Du Pont De Nemours And Company AlN and AlN-containing composites
US5069626A (en) 1987-07-01 1991-12-03 Western Digital Corporation Plated plastic castellated interconnect for electrical components
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5362972A (en) 1990-04-20 1994-11-08 Hitachi, Ltd. Semiconductor device using whiskers
US5164687A (en) 1991-06-17 1992-11-17 Renaissance Electronics Corp. Compact lumped constant non-reciprocal circuit element
US5294295A (en) 1991-10-31 1994-03-15 Vlsi Technology, Inc. Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges
JP2821830B2 (ja) 1992-05-14 1998-11-05 セイコーインスツルメンツ株式会社 半導体薄膜素子その応用装置および半導体薄膜素子の製造方法
DE69333545T2 (de) 1992-12-24 2005-08-25 Canon K.K. Kunststoffzusatzmittel, Kunststoffzusammensetzung und Kunststoffformmasse, die dieses enthalten
US5459368A (en) 1993-08-06 1995-10-17 Matsushita Electric Industrial Co., Ltd. Surface acoustic wave device mounted module
DE4329696C2 (de) 1993-09-02 1995-07-06 Siemens Ag Auf Leiterplatten oberflächenmontierbares Multichip-Modul mit SMD-fähigen Anschlußelementen
US5391257A (en) 1993-12-10 1995-02-21 Rockwell International Corporation Method of transferring a thin film to an alternate substrate
FI952093A0 (fi) 1994-05-02 1995-05-02 Siemens Matsushita Components Kapsling foer med akustiska ytvaogefunktionerande byggelement
US6124179A (en) 1996-09-05 2000-09-26 Adamic, Jr.; Fred W. Inverted dielectric isolation process
JP3301262B2 (ja) 1995-03-28 2002-07-15 松下電器産業株式会社 弾性表面波装置
US5729075A (en) 1995-06-12 1998-03-17 National Semiconductor Corporation Tuneable microelectromechanical system resonator
US6013948A (en) 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US6137125A (en) 1995-12-21 2000-10-24 The Whitaker Corporation Two layer hermetic-like coating for on-wafer encapsulatuon of GaAs MMIC's having flip-chip bonding capabilities
DE69718693T2 (de) 1996-03-08 2003-11-27 Matsushita Electric Industrial Co., Ltd. Elektronisches Bauteil und Herstellungsverfahren
US5709960A (en) 1996-06-21 1998-01-20 Motorola, Inc. Mold compound
US6250192B1 (en) 1996-11-12 2001-06-26 Micron Technology, Inc. Method for sawing wafers employing multiple indexing techniques for multiple die dimensions
US6117705A (en) 1997-04-18 2000-09-12 Amkor Technology, Inc. Method of making integrated circuit package having adhesive bead supporting planar lid above planar substrate
JPH11220077A (ja) 1997-10-15 1999-08-10 Toshiba Corp 半導体装置および半導体装置の製造方法
KR100253363B1 (ko) 1997-12-02 2000-04-15 김영환 반도체 패키지용 기판과 그 기판을 이용한 랜드 그리드 어레이반도체 패키지 및 그들의 제조 방법
JP3565547B2 (ja) 1998-07-31 2004-09-15 シャープ株式会社 カラー液晶表示装置およびその製造方法
FR2784261B1 (fr) 1998-10-05 2001-07-27 Ge Medical Syst Sa Materiau d'isolation electrique et de refroidissement de conductivite thermique accrue et application a l'isolation d'un dispositif d'alimentation haute tension
US6236061B1 (en) 1999-01-08 2001-05-22 Lakshaman Mahinda Walpita Semiconductor crystallization on composite polymer substrates
US6696901B1 (en) 1999-03-26 2004-02-24 Hitachi Metals, Ltd. Concentrated constant irreciprocal device
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6154366A (en) 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
JP4528397B2 (ja) 1999-12-17 2010-08-18 ポリマテック株式会社 接着方法および電子部品
US6426559B1 (en) 2000-06-29 2002-07-30 National Semiconductor Corporation Miniature 3D multi-chip module
JP2002093957A (ja) 2000-09-11 2002-03-29 Sony Corp 電子回路装置およびその製造方法
US6713859B1 (en) 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
JP3875477B2 (ja) 2000-09-25 2007-01-31 株式会社東芝 半導体素子
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US6377112B1 (en) 2000-12-05 2002-04-23 Semiconductor Components Industries Llc Circuit and method for PMOS device N-well bias control
US20020070443A1 (en) 2000-12-08 2002-06-13 Xiao-Chun Mu Microelectronic package having an integrated heat sink and build-up layers
US6555906B2 (en) 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
JP4673986B2 (ja) 2001-02-23 2011-04-20 星和電機株式会社 表面実装方発光ダイオードの製造方法
US6703688B1 (en) 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6943429B1 (en) 2001-03-08 2005-09-13 Amkor Technology, Inc. Wafer having alignment marks extending from a first to a second surface of the wafer
US6706553B2 (en) 2001-03-26 2004-03-16 Intel Corporation Dispensing process for fabrication of microelectronic packages
US6596570B2 (en) 2001-06-06 2003-07-22 International Business Machines Corporation SOI device with reduced junction capacitance
US7332819B2 (en) 2002-01-09 2008-02-19 Micron Technology, Inc. Stacked die in die BGA package
US6841413B2 (en) 2002-01-07 2005-01-11 Intel Corporation Thinned die integrated circuit package
TW577160B (en) 2002-02-04 2004-02-21 Casio Computer Co Ltd Semiconductor device and manufacturing method thereof
DE10206919A1 (de) 2002-02-19 2003-08-28 Infineon Technologies Ag Verfahren zur Erzeugung einer Abdeckung, Verfahren zum Herstellen eines gehäusten Bauelements
KR100476901B1 (ko) 2002-05-22 2005-03-17 삼성전자주식회사 소이 반도체기판의 형성방법
FR2842832B1 (fr) 2002-07-24 2006-01-20 Lumilog Procede de realisation par epitaxie en phase vapeur d'un film de nitrure de gallium a faible densite de defaut
US7042072B1 (en) 2002-08-02 2006-05-09 Amkor Technology, Inc. Semiconductor package and method of manufacturing the same which reduces warpage
US20040021152A1 (en) 2002-08-05 2004-02-05 Chanh Nguyen Ga/A1GaN Heterostructure Field Effect Transistor with dielectric recessed gate
KR100480273B1 (ko) 2002-11-07 2005-04-07 삼성전자주식회사 실리콘-유리 양극 접합 기술을 이용한 광섬유 블록의 제조방법
US7710771B2 (en) 2002-11-20 2010-05-04 The Regents Of The University Of California Method and apparatus for capacitorless double-gate storage
US7067909B2 (en) 2002-12-31 2006-06-27 Massachusetts Institute Of Technology Multi-layer integrated semiconductor structure having an electrical shielding portion
US6855606B2 (en) 2003-02-20 2005-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-rod devices
KR100486627B1 (ko) 2003-02-21 2005-05-03 엘지전자 주식회사 반도체 패키지
US6911379B2 (en) 2003-03-05 2005-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming strained silicon on insulator substrate
JP2004273604A (ja) 2003-03-06 2004-09-30 Fujitsu Ltd 半導体装置と半導体電子部品との製造方法と半導体電子部品
JP3917946B2 (ja) 2003-03-11 2007-05-23 富士通株式会社 積層型半導体装置
US6753239B1 (en) 2003-04-04 2004-06-22 Xilinx, Inc. Bond and back side etchback transistor fabrication process
US6864156B1 (en) 2003-04-04 2005-03-08 Xilinx, Inc. Semiconductor wafer with well contacts on back side
JP3826898B2 (ja) 2003-04-22 2006-09-27 松下電工株式会社 電子部品の製造方法及び半導体装置
US7109635B1 (en) 2003-06-11 2006-09-19 Sawtek, Inc. Wafer level packaging of materials with different coefficients of thermal expansion
US7596849B1 (en) 2003-06-11 2009-10-06 Triquint Semiconductor, Inc. Method of assembling a wafer-level package filter
US6951775B2 (en) 2003-06-28 2005-10-04 International Business Machines Corporation Method for forming interconnects on thin wafers
WO2005010987A1 (ja) 2003-07-24 2005-02-03 Matsushita Electric Industrial Co., Ltd. 球状半導体素子埋設配線板
JP2005064188A (ja) 2003-08-11 2005-03-10 Sumitomo Electric Ind Ltd 基板の回収方法および再生方法、ならびに半導体ウエハの製造方法
FR2860919B1 (fr) 2003-10-09 2009-09-11 St Microelectronics Sa Structures et procedes de fabrication de regions semiconductrices sur isolant
WO2005063876A1 (ja) 2003-12-25 2005-07-14 Jsr Corporation 熱可塑性エラストマー組成物およびその製造方法並びに成形品
US7489032B2 (en) 2003-12-25 2009-02-10 Casio Computer Co., Ltd. Semiconductor device including a hard sheet to reduce warping of a base plate and method of fabricating the same
US20060124961A1 (en) 2003-12-26 2006-06-15 Canon Kabushiki Kaisha Semiconductor substrate, manufacturing method thereof, and semiconductor device
JP4271590B2 (ja) 2004-01-20 2009-06-03 新光電気工業株式会社 半導体装置及びその製造方法
JP3945483B2 (ja) 2004-01-27 2007-07-18 カシオ計算機株式会社 半導体装置の製造方法
US6992400B2 (en) 2004-01-30 2006-01-31 Nokia Corporation Encapsulated electronics device with improved heat dissipation
US20050212419A1 (en) 2004-03-23 2005-09-29 Eastman Kodak Company Encapsulating oled devices
JP3925809B2 (ja) 2004-03-31 2007-06-06 カシオ計算機株式会社 半導体装置およびその製造方法
US7312261B2 (en) 2004-05-11 2007-12-25 International Business Machines Corporation Thermal interface adhesive and rework
JP2005327984A (ja) 2004-05-17 2005-11-24 Shinko Electric Ind Co Ltd 電子部品及び電子部品実装構造の製造方法
US7307346B2 (en) 2004-05-18 2007-12-11 Infineon Technologies Ag Final passivation scheme for integrated circuits
US6864540B1 (en) 2004-05-21 2005-03-08 International Business Machines Corp. High performance FET with elevated source/drain region
JP4398305B2 (ja) 2004-06-02 2010-01-13 カシオ計算機株式会社 半導体装置およびその製造方法
JP3801601B2 (ja) 2004-06-15 2006-07-26 シャープ株式会社 蓋部を備えた半導体ウェハの製造方法及び半導体装置の製造方法
US7488690B2 (en) 2004-07-06 2009-02-10 Applied Materials, Inc. Silicon nitride film with stress control
US7238560B2 (en) 2004-07-23 2007-07-03 Cree, Inc. Methods of fabricating nitride-based transistors with a cap layer and a recessed gate
US7591958B2 (en) 2004-09-14 2009-09-22 Stmicroelectronics Sa Thin glass chip for an electronic component and manufacturing method
US20060099733A1 (en) 2004-11-09 2006-05-11 Geefay Frank S Semiconductor package and fabrication method
US7098070B2 (en) 2004-11-16 2006-08-29 International Business Machines Corporation Device and method for fabricating double-sided SOI wafer scale package with through via connections
US7547605B2 (en) 2004-11-22 2009-06-16 Taiwan Semiconductor Manufacturing Company Microelectronic device and a method for its manufacture
TWI259538B (en) 2004-11-22 2006-08-01 Au Optronics Corp Thin film transistor and fabrication method thereof
US7519257B2 (en) 2004-11-24 2009-04-14 Cornell Research Foundation, Inc. Waveguide structure for guiding light in low-index material
JP4581768B2 (ja) 2005-03-16 2010-11-17 ソニー株式会社 半導体装置の製造方法
US7393770B2 (en) 2005-05-19 2008-07-01 Micron Technology, Inc. Backside method for fabricating semiconductor components with conductive interconnects
US7619347B1 (en) 2005-05-24 2009-11-17 Rf Micro Devices, Inc. Layer acoustic wave device and method of making the same
CN101107776B (zh) 2005-06-16 2010-05-19 株式会社村田制作所 压电器件及其制作方法
US20080076371A1 (en) 2005-07-11 2008-03-27 Alexander Dribinsky Circuit and method for controlling charge injection in radio frequency switches
JP4815935B2 (ja) 2005-08-02 2011-11-16 日立電線株式会社 モールド成形体の製造方法
US7247542B2 (en) 2005-08-10 2007-07-24 Integrated Crystal Technology, Inc. Fabrication method of spiral inductor on porous glass substrate
EP1917679A2 (en) 2005-08-26 2008-05-07 MEMC Electronic Materials, Inc. Method for the manufacture of a strained silicon-on-insulator structure
JP4644577B2 (ja) 2005-09-30 2011-03-02 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
US8465175B2 (en) 2005-11-29 2013-06-18 GE Lighting Solutions, LLC LED lighting assemblies with thermal overmolding
US20070122943A1 (en) 2005-11-30 2007-05-31 Foong Chee S Method of making semiconductor package having exposed heat spreader
US20090298219A1 (en) 2005-12-26 2009-12-03 Sharp Kabushiki Kaisha Method for Manufacturing Solid-State Image Pickup Device Module
US20070194342A1 (en) 2006-01-12 2007-08-23 Kinzer Daniel M GaN SEMICONDUCTOR DEVICE AND PROCESS EMPLOYING GaN ON THIN SAPHIRE LAYER ON POLYCRYSTALLINE SILICON CARBIDE
JP4476939B2 (ja) 2006-01-12 2010-06-09 株式会社東芝 半導体装置
US20070190747A1 (en) 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level packaging to lidded chips
US7863727B2 (en) 2006-02-06 2011-01-04 Micron Technology, Inc. Microelectronic devices and methods for manufacturing microelectronic devices
JP4591378B2 (ja) 2006-02-21 2010-12-01 株式会社デンソー 半導体装置の製造方法
US20070243662A1 (en) 2006-03-17 2007-10-18 Johnson Donald W Packaging of MEMS devices
KR101478810B1 (ko) 2006-07-28 2015-01-02 가부시키가이샤 한도오따이 에네루기 켄큐쇼 축전 장치
US7569422B2 (en) 2006-08-11 2009-08-04 Megica Corporation Chip package and method for fabricating the same
KR20080017965A (ko) 2006-08-23 2008-02-27 삼성전자주식회사 가요성 표시 장치용 표시판의 제조 방법
US7749882B2 (en) 2006-08-23 2010-07-06 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US7816231B2 (en) 2006-08-29 2010-10-19 International Business Machines Corporation Device structures including backside contacts, and methods for forming same
US7960218B2 (en) 2006-09-08 2011-06-14 Wisconsin Alumni Research Foundation Method for fabricating high-speed thin-film transistors
JP5018066B2 (ja) 2006-12-19 2012-09-05 信越半導体株式会社 歪Ｓｉ基板の製造方法
US20080157303A1 (en) 2006-12-28 2008-07-03 Advanced Chip Engineering Technology Inc. Structure of super thin chip scale package and method of the same
US7888742B2 (en) 2007-01-10 2011-02-15 International Business Machines Corporation Self-aligned metal-semiconductor alloy and metallization for sub-lithographic source and drain contacts
JP2008235490A (ja) 2007-03-19 2008-10-02 Sumitomo Bakelite Co Ltd 中空構造体の製造方法および中空構造体
US20080251927A1 (en) 2007-04-13 2008-10-16 Texas Instruments Incorporated Electromigration-Resistant Flip-Chip Solder Joints
US7960772B2 (en) 2007-04-26 2011-06-14 Peregrine Semiconductor Corporation Tuning capacitance to enhance FET stack voltage withstand
US8183151B2 (en) 2007-05-04 2012-05-22 Micron Technology, Inc. Methods of forming conductive vias through substrates, and structures and assemblies resulting therefrom
KR100923562B1 (ko) 2007-05-08 2009-10-27 삼성전자주식회사 반도체 패키지 및 그 형성방법
US20080277778A1 (en) 2007-05-10 2008-11-13 Furman Bruce K Layer Transfer Process and Functionally Enhanced Integrated Circuits Products Thereby
US7955955B2 (en) 2007-05-10 2011-06-07 International Business Machines Corporation Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures
JP2008279567A (ja) 2007-05-11 2008-11-20 Denso Corp 半導体装置の製造方法
US7553752B2 (en) 2007-06-20 2009-06-30 Stats Chippac, Ltd. Method of making a wafer level integration package
KR20090004147A (ko) 2007-07-06 2009-01-12 삼성전자주식회사 반도체 소자 및 그 형성 방법
US20090014856A1 (en) 2007-07-10 2009-01-15 International Business Machine Corporation Microbump seal
JP5013467B2 (ja) 2007-07-18 2012-08-29 株式会社デンソー 半導体装置の製造方法
US9391588B2 (en) 2007-08-31 2016-07-12 Rf Micro Devices, Inc. MEMS vibrating structure using an orientation dependent single-crystal piezoelectric thin film layer
US20090072382A1 (en) 2007-09-18 2009-03-19 Guzek John S Microelectronic package and method of forming same
US9941245B2 (en) 2007-09-25 2018-04-10 Intel Corporation Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate
US7704844B2 (en) 2007-10-04 2010-04-27 International Business Machines Corporation High performance MOSFET
US7868419B1 (en) 2007-10-18 2011-01-11 Rf Micro Devices, Inc. Linearity improvements of semiconductor substrate based radio frequency devices
US7790543B2 (en) 2008-01-11 2010-09-07 International Business Machines Corporation Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures
JP4840373B2 (ja) 2008-01-31 2011-12-21 カシオ計算機株式会社 半導体装置およびその製造方法
JP4568337B2 (ja) 2008-02-22 2010-10-27 株式会社東芝 集積半導体装置
US7749814B2 (en) 2008-03-13 2010-07-06 Stats Chippac, Ltd. Semiconductor device with integrated passive circuit and method of making the same using sacrificial substrate
JP4666028B2 (ja) 2008-03-31 2011-04-06 カシオ計算機株式会社 半導体装置
US20110102002A1 (en) 2008-04-09 2011-05-05 Riehl Bill L Electrode and sensor having carbon nanostructures
JP5415823B2 (ja) 2008-05-16 2014-02-12 株式会社デンソー 電子回路装置及びその製造方法
US7745920B2 (en) 2008-06-10 2010-06-29 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US20100012354A1 (en) 2008-07-14 2010-01-21 Logan Brook Hedin Thermally conductive polymer based printed circuit board
US8236609B2 (en) 2008-08-01 2012-08-07 Freescale Semiconductor, Inc. Packaging an integrated circuit die with backside metallization
US7843072B1 (en) 2008-08-12 2010-11-30 Amkor Technology, Inc. Semiconductor package having through holes
JP4638530B2 (ja) 2008-08-19 2011-02-23 日本電波工業株式会社 圧電部品及びその製造方法
US20100081237A1 (en) 2008-09-30 2010-04-01 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Integrated Circuit Assemblies and Methods for Encapsulating a Semiconductor Device
US8173547B2 (en) 2008-10-23 2012-05-08 Lam Research Corporation Silicon etch with passivation using plasma enhanced oxidation
US9059174B2 (en) 2008-11-05 2015-06-16 Stmicroelectronics, Inc. Method to reduce metal fuse thickness without extra mask
JP5161732B2 (ja) 2008-11-11 2013-03-13 新光電気工業株式会社 半導体装置の製造方法
JP5468242B2 (ja) 2008-11-21 2014-04-09 株式会社東芝 Ｍｅｍｓパッケージおよびｍｅｍｓパッケージの製造方法
US7927904B2 (en) 2009-01-05 2011-04-19 Dalsa Semiconductor Inc. Method of making BIOMEMS devices
JP5556072B2 (ja) 2009-01-07 2014-07-23 ソニー株式会社 半導体装置、その製造方法、ミリ波誘電体内伝送装置
WO2010080068A1 (en) 2009-01-12 2010-07-15 Ravi Kanth Kolan Method for manufacturing a low cost three dimensional stack package and resulting structures using through silicon vias and assemblies
JP4984179B2 (ja) 2009-02-06 2012-07-25 ソニー株式会社 半導体装置
KR101282995B1 (ko) 2009-05-27 2013-07-04 (주)파트론 비가역 회로소자
US8508056B2 (en) 2009-06-16 2013-08-13 Dongbu Hitek Co., Ltd. Heat releasing semiconductor package, method for manufacturing the same, and display apparatus including the same
JP5175803B2 (ja) 2009-07-01 2013-04-03 新光電気工業株式会社 半導体装置の製造方法
KR101169531B1 (ko) * 2009-07-03 2012-07-27 가부시키가이샤 테라미크로스 반도체구성체 및 그 제조방법과 반도체장치 및 그 제조방법
US8921168B2 (en) 2009-07-15 2014-12-30 Silanna Semiconductor U.S.A., Inc. Thin integrated circuit chip-on-board assembly and method of making
US8067833B2 (en) 2009-07-23 2011-11-29 Raytheon Company Low noise high thermal conductivity mixed signal package
US8432016B1 (en) 2009-07-29 2013-04-30 Rf Micro Devices, Inc. Stacked body-contacted field effect transistor
TWI515869B (zh) 2009-07-30 2016-01-01 高通公司 系統級封裝
CN102484155A (zh) 2009-08-17 2012-05-30 第一太阳能有限公司 阻挡层
US8164158B2 (en) 2009-09-11 2012-04-24 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device
US8362599B2 (en) 2009-09-24 2013-01-29 Qualcomm Incorporated Forming radio frequency integrated circuits
US8791532B2 (en) 2009-11-18 2014-07-29 Sensirion Ag Sensor mounted in flip-chip technology on a substrate
US9202769B2 (en) 2009-11-25 2015-12-01 Stats Chippac, Ltd. Semiconductor device and method of forming thermal lid for balancing warpage and thermal management
JP5581519B2 (ja) 2009-12-04 2014-09-03 新光電気工業株式会社 半導体パッケージとその製造方法
CN102088014A (zh) 2009-12-04 2011-06-08 中国科学院微电子研究所 3d集成电路结构、半导体器件及其形成方法
US8299633B2 (en) 2009-12-21 2012-10-30 Advanced Micro Devices, Inc. Semiconductor chip device with solder diffusion protection
US8030145B2 (en) 2010-01-08 2011-10-04 International Business Machines Corporation Back-gated fully depleted SOI transistor
US9576919B2 (en) 2011-12-30 2017-02-21 Deca Technologies Inc. Semiconductor device and method comprising redistribution layers
US9196509B2 (en) 2010-02-16 2015-11-24 Deca Technologies Inc Semiconductor device and method of adaptive patterning for panelized packaging
JP5544986B2 (ja) 2010-04-01 2014-07-09 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法、及び貼り合わせｓｏｉウェーハ
US9431316B2 (en) 2010-05-04 2016-08-30 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming channels in back surface of FO-WLCSP for heat dissipation
JP5584011B2 (ja) 2010-05-10 2014-09-03 新光電気工業株式会社 半導体パッケージの製造方法
JP2011243596A (ja) 2010-05-14 2011-12-01 Panasonic Corp パッケージ部品の製造方法およびパッケージ部品
JP2011248072A (ja) 2010-05-26 2011-12-08 Hitachi Displays Ltd 画像表示装置の製造方法
US8557679B2 (en) 2010-06-30 2013-10-15 Corning Incorporated Oxygen plasma conversion process for preparing a surface for bonding
KR101698932B1 (ko) 2010-08-17 2017-01-23 삼성전자 주식회사 반도체 패키지 및 그 제조방법
US8551798B2 (en) 2010-09-21 2013-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Microstructure with an enhanced anchor
JP2012089566A (ja) 2010-10-15 2012-05-10 Elpida Memory Inc 半導体装置及びその製造方法、並びにデータ処理システム
US20120094418A1 (en) 2010-10-18 2012-04-19 Triquint Semiconductor, Inc. Wafer Level Package and Manufacturing Method Using Photodefinable Polymer for Enclosing Acoustic Devices
US8716051B2 (en) 2010-10-21 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS device with release aperture
CN102456737B (zh) 2010-10-27 2016-03-30 中国科学院微电子研究所 半导体结构及其制造方法
KR20120053332A (ko) 2010-11-17 2012-05-25 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
JP5703010B2 (ja) 2010-12-16 2015-04-15 新光電気工業株式会社 半導体パッケージ及びその製造方法
US8492210B2 (en) 2010-12-17 2013-07-23 Institute of Microelectronics, Chinese Academy of Sciences Transistor, semiconductor device comprising the transistor and method for manufacturing the same
US8716800B2 (en) 2010-12-31 2014-05-06 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor structure and method for manufacturing the same
US8917510B2 (en) 2011-01-14 2014-12-23 International Business Machines Corporation Reversibly adhesive thermal interface material
JP5715835B2 (ja) 2011-01-25 2015-05-13 新光電気工業株式会社 半導体パッケージ及びその製造方法
US8420447B2 (en) 2011-03-23 2013-04-16 Stats Chippac Ltd. Integrated circuit packaging system with flipchip leadframe and method of manufacture thereof
US8399957B2 (en) 2011-04-08 2013-03-19 International Business Machines Corporation Dual-depth self-aligned isolation structure for a back gate electrode
US8507989B2 (en) 2011-05-16 2013-08-13 International Business Machine Corporation Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance
US8415743B2 (en) 2011-05-24 2013-04-09 International Business Machines Corporation ETSOI CMOS with back gates
TWI575684B (zh) 2011-06-13 2017-03-21 矽品精密工業股份有限公司 晶片尺寸封裝件
US9633854B2 (en) 2011-06-23 2017-04-25 Institute of Microelectronics, Chinese Academy of Sciences MOSFET and method for manufacturing the same
US8772853B2 (en) 2011-07-12 2014-07-08 The Regents Of The University Of California All graphene flash memory device
US9390364B2 (en) 2011-08-08 2016-07-12 Féinics Amatech Teoranta Transponder chip module with coupling frame on a common substrate for secure and non-secure smartcards and tags
US20130037929A1 (en) 2011-08-09 2013-02-14 Kay S. Essig Stackable wafer level packages and related methods
US9064883B2 (en) * 2011-08-25 2015-06-23 Intel Mobile Communications GmbH Chip with encapsulated sides and exposed surface
CN102983116B (zh) 2011-09-07 2015-09-30 中国科学院微电子研究所 半导体衬底、具有该半导体衬底的集成电路及其制造方法
US8963321B2 (en) 2011-09-12 2015-02-24 Infineon Technologies Ag Semiconductor device including cladded base plate
CN103000537B (zh) 2011-09-15 2015-12-09 万国半导体股份有限公司 一种晶圆级的封装结构及其制备方法
CN103000671B (zh) 2011-09-16 2015-07-15 中国科学院微电子研究所 Mosfet及其制造方法
US8803242B2 (en) 2011-09-19 2014-08-12 Eta Semiconductor Inc. High mobility enhancement mode FET
KR101906408B1 (ko) 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9368429B2 (en) 2011-10-25 2016-06-14 Intel Corporation Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips
US9190391B2 (en) 2011-10-26 2015-11-17 Maxim Integrated Products, Inc. Three-dimensional chip-to-wafer integration
US8664044B2 (en) 2011-11-02 2014-03-04 Stmicroelectronics Pte Ltd. Method of fabricating land grid array semiconductor package
US8643148B2 (en) 2011-11-30 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer structures and methods for forming the same
KR20130064289A (ko) 2011-12-08 2013-06-18 에스케이하이닉스 주식회사 반도체 소자 및 그 제조 방법
US20130193445A1 (en) 2012-01-26 2013-08-01 International Business Machines Corporation Soi structures including a buried boron nitride dielectric
JP2013162096A (ja) 2012-02-08 2013-08-19 Fujitsu Semiconductor Ltd 半導体チップの製造方法及びラミネート装置
KR101918608B1 (ko) 2012-02-28 2018-11-14 삼성전자 주식회사 반도체 패키지
JP6214132B2 (ja) 2012-02-29 2017-10-18 キヤノン株式会社 光電変換装置、撮像システムおよび光電変換装置の製造方法
JP5558595B2 (ja) 2012-03-14 2014-07-23 株式会社東芝 半導体装置及び半導体装置の製造方法
JP2013222745A (ja) 2012-04-13 2013-10-28 Ibiden Co Ltd 電子部品及びその製造方法
US8835978B2 (en) 2012-05-14 2014-09-16 Infineon Technologies Ag Lateral transistor on polymer
JP5903337B2 (ja) 2012-06-08 2016-04-13 新光電気工業株式会社 半導体パッケージ及びその製造方法
US8698323B2 (en) 2012-06-18 2014-04-15 Invensas Corporation Microelectronic assembly tolerant to misplacement of microelectronic elements therein
US8653467B2 (en) 2012-06-19 2014-02-18 Raytheon Company Multichip packaging for imaging system
US8563403B1 (en) 2012-06-27 2013-10-22 International Business Machines Corporation Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
US9219032B2 (en) 2012-07-09 2015-12-22 Qualcomm Incorporated Integrating through substrate vias from wafer backside layers of integrated circuits
US8878360B2 (en) 2012-07-13 2014-11-04 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip
US8653626B2 (en) 2012-07-18 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures including a capacitor and methods of forming the same
US8963336B2 (en) 2012-08-03 2015-02-24 Samsung Electronics Co., Ltd. Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
KR101970291B1 (ko) 2012-08-03 2019-04-18 삼성전자주식회사 반도체 패키지의 제조 방법
JP6024400B2 (ja) 2012-11-07 2016-11-16 ソニー株式会社 半導体装置、半導体装置の製造方法、及びアンテナスイッチモジュール
US8796072B2 (en) 2012-11-15 2014-08-05 Amkor Technology, Inc. Method and system for a semiconductor device package with a die-to-die first bond
US9431369B2 (en) 2012-12-13 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Antenna apparatus and method
US8927405B2 (en) 2012-12-18 2015-01-06 International Business Machines Corporation Accurate control of distance between suspended semiconductor nanowires and substrate surface
KR102031731B1 (ko) 2012-12-18 2019-10-14 삼성전자주식회사 반도체 패키지 및 이의 제조방법
US8786105B1 (en) 2013-01-11 2014-07-22 Intel Mobile Communications GmbH Semiconductor device with chip having low-k-layers
US9733428B2 (en) 2013-02-04 2017-08-15 American Semiconductor, Inc. Flexible 3-D photonic device
US9812350B2 (en) * 2013-03-06 2017-11-07 Qorvo Us, Inc. Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
US20140306324A1 (en) 2013-03-06 2014-10-16 Rf Micro Devices, Inc. Semiconductor device with a polymer substrate and methods of manufacturing the same
US9583414B2 (en) 2013-10-31 2017-02-28 Qorvo Us, Inc. Silicon-on-plastic semiconductor device and method of making the same
US9214337B2 (en) 2013-03-06 2015-12-15 Rf Micro Devices, Inc. Patterned silicon-on-plastic (SOP) technology and methods of manufacturing the same
US20140252566A1 (en) 2013-03-06 2014-09-11 Rf Micro Devices, Inc. Silicon-on-dual plastic (sodp) technology and methods of manufacturing the same
US8941248B2 (en) 2013-03-13 2015-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device package and method
US8987876B2 (en) 2013-03-14 2015-03-24 General Electric Company Power overlay structure and method of making same
US9070660B2 (en) 2013-03-15 2015-06-30 Intel Corporation Polymer thermal interface material having enhanced thermal conductivity
US9111941B2 (en) 2013-03-15 2015-08-18 Globalfoundries Singapore Pte. Ltd. Non-volatile memory device with TSI/TSV application
JP6596412B2 (ja) 2013-03-22 2019-10-23 ヘンケル アイピー アンド ホールディング ゲゼルシャフト ミット ベシュレンクテル ハフツング ジエン／ジエノフィル対および補修性を有する熱硬化性樹脂組成物
US9349700B2 (en) 2013-04-24 2016-05-24 Stats Chippac, Ltd. Semiconductor device and method of forming stress-reduced conductive joint structures
CN105144385B (zh) 2013-04-26 2018-06-29 奥林巴斯株式会社 摄像装置
US9467192B2 (en) 2013-04-29 2016-10-11 Broadcom Corporation MCM integration and power amplifier matching of non-reciprocal devices
US9275916B2 (en) 2013-05-03 2016-03-01 Infineon Technologies Ag Removable indicator structure in electronic chips of a common substrate for process adjustment
EP3000062A4 (en) 2013-05-20 2017-01-11 Synopsys, Inc. Semi-local ballistic mobility model
US9281198B2 (en) 2013-05-23 2016-03-08 GlobalFoundries, Inc. Method of fabricating a semiconductor device including embedded crystalline back-gate bias planes
KR102130700B1 (ko) 2013-05-30 2020-07-07 삼성디스플레이 주식회사 표시장치용 윈도우 및 이를 포함하는 표시 장치
TWI508255B (zh) 2013-07-01 2015-11-11 Powertech Technology Inc 散熱型覆晶封裝構造
US9059123B2 (en) 2013-07-24 2015-06-16 International Business Machines Corporation Active matrix using hybrid integrated circuit and bipolar transistor
JP6292049B2 (ja) 2013-09-02 2018-03-14 ソニー株式会社 半導体装置およびその製造方法
US20150060956A1 (en) 2013-09-03 2015-03-05 Windtop Technology Corp. Integrated mems pressure sensor with mechanical electrical isolation
US9806422B2 (en) 2013-09-11 2017-10-31 International Business Machines Corporation Antenna-in-package structures with broadside and end-fire radiations
US9142432B2 (en) * 2013-09-13 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package structures with recesses in molding compound
JP6372898B2 (ja) 2013-10-15 2018-08-15 インテル・コーポレーション 磁気遮蔽集積回路パッケージ
US9627287B2 (en) 2013-10-18 2017-04-18 Infineon Technologies Ag Thinning in package using separation structure as stop
US9576930B2 (en) 2013-11-08 2017-02-21 Taiwan Semiconductor Manufacturing Co., Ltd. Thermally conductive structure for heat dissipation in semiconductor packages
CN103560110B (zh) * 2013-11-22 2016-02-17 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN103730429B (zh) 2013-12-05 2017-06-20 通富微电子股份有限公司 封装结构
US9269694B2 (en) 2013-12-11 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with thermal management features for reduced thermal crosstalk and methods of forming same
US9184128B2 (en) 2013-12-13 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package and methods of forming the same
US9352956B2 (en) 2014-01-16 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS devices and methods for forming same
US10658358B2 (en) 2015-03-09 2020-05-19 Monolithic 3D Inc. 3D semiconductor wafer, devices, and structure
US9653443B2 (en) 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9368455B2 (en) 2014-03-28 2016-06-14 Intel Corporation Electromagnetic interference shield for semiconductor chip packages
US20150311132A1 (en) 2014-04-28 2015-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Scribe line structure and method of forming same
US9165793B1 (en) 2014-05-02 2015-10-20 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9449837B2 (en) 2014-05-09 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process
US10141201B2 (en) 2014-06-13 2018-11-27 Taiwan Semiconductor Manufacturing Company Integrated circuit packages and methods of forming same
KR102245003B1 (ko) 2014-06-27 2021-04-28 삼성전자주식회사 오버행을 극복할 수 있는 반도체 패키지 및 그 제조방법
US9397118B2 (en) 2014-06-30 2016-07-19 International Business Machines Corporation Thin-film ambipolar logic
CN107004639B (zh) 2014-07-08 2021-02-05 麻省理工学院 衬底制造方法
EP2996143B1 (en) 2014-09-12 2018-12-26 Qorvo US, Inc. Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same
US20160079233A1 (en) 2014-09-15 2016-03-17 Infineon Technologies Austria Ag Iii-v semiconductor material based ac switch
US10085352B2 (en) * 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US9530709B2 (en) 2014-11-03 2016-12-27 Qorvo Us, Inc. Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
KR101647559B1 (ko) * 2014-11-07 2016-08-10 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 제조 방법 및 반도체 패키지
KR102211143B1 (ko) 2014-11-13 2021-02-02 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9536853B2 (en) 2014-11-18 2017-01-03 International Business Machines Corporation Semiconductor device including built-in crack-arresting film structure
JP6233285B2 (ja) 2014-11-28 2017-11-22 三菱電機株式会社 半導体モジュール、電力変換装置
DE102014117594A1 (de) 2014-12-01 2016-06-02 Infineon Technologies Ag Halbleiter-Package und Verfahren zu seiner Herstellung
US9548273B2 (en) 2014-12-04 2017-01-17 Invensas Corporation Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies
TWI540371B (zh) 2015-03-03 2016-07-01 群創光電股份有限公司 顯示面板及顯示裝置
CN107408532A (zh) 2015-03-17 2017-11-28 太阳能爱迪生半导体有限公司 用于绝缘体上半导体结构的制造的热稳定电荷捕获层
US9960145B2 (en) * 2015-03-25 2018-05-01 Qorvo Us, Inc. Flip chip module with enhanced properties
US9613831B2 (en) 2015-03-25 2017-04-04 Qorvo Us, Inc. Encapsulated dies with enhanced thermal performance
US9875971B2 (en) 2015-03-26 2018-01-23 Globalfoundries Singapore Pte. Ltd. Magnetic shielding of MRAM package
KR102392202B1 (ko) 2015-04-09 2022-05-02 삼성전자주식회사 방열막을 구비한 반도체 패키지 및 그 제조방법
US9653428B1 (en) 2015-04-14 2017-05-16 Amkor Technology, Inc. Semiconductor package and fabricating method thereof
CN106158786A (zh) 2015-04-15 2016-11-23 力成科技股份有限公司 半导体封装体及其制作方法
US20160343604A1 (en) 2015-05-22 2016-11-24 Rf Micro Devices, Inc. Substrate structure with embedded layer for post-processing silicon handle elimination
US9969614B2 (en) 2015-05-29 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS packages and methods of manufacture thereof
US9815685B2 (en) 2015-06-15 2017-11-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor sensing structure and manufacturing method thereof
EP3113216B1 (en) 2015-07-01 2021-05-19 IMEC vzw A method for bonding and interconnecting integrated circuit devices
US9461001B1 (en) 2015-07-22 2016-10-04 Advanced Semiconductor Engineering, Inc. Semiconductor device package integrated with coil for wireless charging and electromagnetic interference shielding, and method of manufacturing the same
US9899285B2 (en) 2015-07-30 2018-02-20 Semtech Corporation Semiconductor device and method of forming small Z semiconductor package
CN107924881B (zh) * 2015-08-18 2020-07-31 三菱电机株式会社 半导体装置
WO2017034929A1 (en) 2015-08-21 2017-03-02 Skyworks Solutions, Inc. Non-uniform spacing in transistor stacks
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US10181428B2 (en) 2015-08-28 2019-01-15 Skyworks Solutions, Inc. Silicon on porous silicon
KR102653044B1 (ko) 2015-09-01 2024-04-01 소니그룹주식회사 적층체
US10276495B2 (en) 2015-09-11 2019-04-30 Qorvo Us, Inc. Backside semiconductor die trimming
US9818659B2 (en) 2015-10-12 2017-11-14 Deca Technologies Inc. Multi-die package comprising unit specific alignment and unit specific routing
US9850126B2 (en) 2015-12-31 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
US10020405B2 (en) 2016-01-19 2018-07-10 Qorvo Us, Inc. Microelectronics package with integrated sensors
US9812451B2 (en) 2016-02-03 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd Field effect transistor contact with reduced contact resistance
TWI629759B (zh) 2016-03-01 2018-07-11 精材科技股份有限公司 晶片封裝體及其製造方法
US10090262B2 (en) 2016-05-09 2018-10-02 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10468329B2 (en) 2016-07-18 2019-11-05 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10103080B2 (en) 2016-06-10 2018-10-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
CN106098609B (zh) 2016-06-20 2019-03-26 西安电子科技大学 基于非晶化与尺度效应的AlN埋绝缘层上晶圆级单轴应变Si的制作方法
US9859254B1 (en) 2016-06-30 2018-01-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and a manufacturing method thereof
US11064609B2 (en) * 2016-08-04 2021-07-13 X Display Company Technology Limited Printable 3D electronic structure
JP7035014B2 (ja) 2016-08-12 2022-03-14 コーボ ユーエス，インコーポレイティド 性能が強化されたウェハレベルパッケージ
US10109550B2 (en) 2016-08-12 2018-10-23 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10486965B2 (en) 2016-08-12 2019-11-26 Qorvo Us, Inc. Wafer-level package with enhanced performance
US9786586B1 (en) 2016-08-21 2017-10-10 Micron Technology, Inc. Semiconductor package and fabrication method thereof
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US11069560B2 (en) 2016-11-01 2021-07-20 Shin-Etsu Chemical Co., Ltd. Method of transferring device layer to transfer substrate and highly thermal conductive substrate
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US20180151461A1 (en) * 2016-11-29 2018-05-31 Globalfoundries Inc. Stiffener for fan-out wafer level packaging and method of manufacturing
US10700011B2 (en) 2016-12-07 2020-06-30 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an integrated SIP module with embedded inductor or package
US10068831B2 (en) * 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
KR102652721B1 (ko) 2016-12-30 2024-03-28 인텔 코포레이션 고주파수 통신을 위한 3d 적층된 초박형 패키지 모듈로 설계된 마이크로 전자 디바이스
GB2574160B (en) 2017-03-13 2022-04-27 Mitsubishi Electric Corp Microwave device and antenna
US10529698B2 (en) 2017-03-15 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming same
US10784348B2 (en) 2017-03-23 2020-09-22 Qualcomm Incorporated Porous semiconductor handle substrate
CN108663909A (zh) 2017-03-27 2018-10-16 台湾积体电路制造股份有限公司 用于光刻图案化的方法
JP7213469B2 (ja) 2017-03-31 2023-01-27 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
US10163831B2 (en) 2017-04-26 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with post passivation structure and fabrication method therefor
US10141225B2 (en) 2017-04-28 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gates of transistors having reduced resistivity
US10460987B2 (en) 2017-05-09 2019-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device with integrated antenna and manufacturing method thereof
US10134837B1 (en) 2017-06-30 2018-11-20 Qualcomm Incorporated Porous silicon post processing
CN107481998B (zh) 2017-07-05 2020-07-07 华为技术有限公司 封装结构和电子装置
US10490471B2 (en) 2017-07-06 2019-11-26 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10128199B1 (en) 2017-07-17 2018-11-13 International Business Machines Corporation Interchip backside connection
US10366972B2 (en) 2017-09-05 2019-07-30 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10410999B2 (en) 2017-12-19 2019-09-10 Amkor Technology, Inc. Semiconductor device with integrated heat distribution and manufacturing method thereof
US11011502B2 (en) 2018-01-19 2021-05-18 Nepes Co., Ltd. Semiconductor package
JP2019134007A (ja) 2018-01-30 2019-08-08 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US20190288006A1 (en) 2018-03-13 2019-09-19 Psemi Corporation Backside Charge Control for FET Integrated Circuits
US10727212B2 (en) 2018-03-15 2020-07-28 Samsung Electronics Co., Ltd. Semiconductor package
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US10497648B2 (en) 2018-04-03 2019-12-03 General Electric Company Embedded electronics package with multi-thickness interconnect structure and method of making same
US12062700B2 (en) 2018-04-04 2024-08-13 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
CN118213279A (zh) 2018-07-02 2024-06-18 Qorvo美国公司 Rf半导体装置及其制造方法
CN116396791A (zh) 2018-07-17 2023-07-07 国立大学法人山梨大学 润滑剂组合物和轴承
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US11251139B2 (en) 2019-01-22 2022-02-15 X-Celeprint Limited Secure integrated-circuit systems
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046570B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12057374B2 (en) 2019-01-23 2024-08-06 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
WO2020153983A1 (en) 2019-01-23 2020-07-30 Qorvo Us, Inc. Rf semiconductor device and manufacturing method thereof
US12125825B2 (en) 2019-01-23 2024-10-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US12129168B2 (en) 2019-12-23 2024-10-29 Qorvo Us, Inc. Microelectronics package with vertically stacked MEMS device and controller device
WO2022186857A1 (en) 2021-03-05 2022-09-09 Qorvo Us, Inc. Selective etching process for si-ge and doped epitaxial silicon

Also Published As

Publication number Publication date
WO2020009759A1 (en) 2020-01-09
TWI848952B (zh) 2024-07-21
CN112534553A (zh) 2021-03-19
EP3818558A1 (en) 2021-05-12
US20200006193A1 (en) 2020-01-02
TW202015193A (zh) 2020-04-16
US20230041651A1 (en) 2023-02-09
US12046535B2 (en) 2024-07-23
CN112534553B (zh) 2024-03-29

Similar Documents

Publication Publication Date Title
CN112534553B (zh) Rf半导体装置及其制造方法
US12062623B2 (en) RF device without silicon handle substrate for enhanced thermal and electrical performance and methods of forming the same
US11152363B2 (en) Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US12125739B2 (en) RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
US10090262B2 (en) Microelectronics package with inductive element and magnetically enhanced mold compound component
US10490471B2 (en) Wafer-level packaging for enhanced performance
US11961813B2 (en) RF devices with enhanced performance and methods of forming the same
US11387157B2 (en) RF devices with enhanced performance and methods of forming the same
US12046483B2 (en) RF devices with enhanced performance and methods of forming the same
US11646289B2 (en) RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US20210188624A1 (en) Microelectronics package with vertically stacked mems device and controller device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination