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2020 – today

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2024
[j32]
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Kari Hepola, Joonas Multanen, Pekka Jääskeläinen:
Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode. IEEE Trans. Computers 73(2): 560-573 (2024)
[j31]
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Barry de Bruin, Kanishkan Vadivel, Mark Wijtvliet, Pekka Jääskeläinen, Henk Corporaal:
R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA. ACM Trans. Reconfigurable Technol. Syst. 17(2): 34:1-34:34 (2024)
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Topi Leppänen, Joonas Multanen, Leevi Leppänen, Pekka Jääskeläinen:
Towards Efficient OpenCL Pipe Specification for Hardware Accelerators. IWOCL 2024: 2:1-2:8
[c84]
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Julius Ikkala, Tuomas Lauttia, Pekka Jääskeläinen, Markku J. Mäkitalo:
Hierarchical Bitmask Implicit Grids for Efficient Point-in-Volume Queries on the GPU. VISIGRAPP (1): GRAPP, HUCAPP, IVAPP 2024: 285-292
[c83]
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Erwan Leria, Markku J. Mäkitalo, Pekka Jääskeläinen, Mårten Sjöström, Tingting Zhang:
Interactive Multi-GPU Light Field Path Tracing Using Multi-Source Spatial Reprojection. VRST 2024: 15:1-15:11
[c82]
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Jakub Zádník, Anthony Trioux, Michel Kieffer, Markku J. Mäkitalo, François-Xavier Coudoux, Patrick Corlay, Pekka Jääskeläinen:
Performance of Linear Coding and Transmission in Low-Latency Computer Vision Offloading. WCNC 2024: 1-6
2023
[j30]
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Topi Leppänen, Atro Lotvonen, Panagiotis Mousouliotis, Joonas Multanen, Georgios Keramidas, Pekka Jääskeläinen:
Efficient OpenCL system integration of non-blocking FPGA accelerators. Microprocess. Microsystems 97: 104772 (2023)
[j29]
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Alex Hirvonen, Topi Leppänen, Kari Hepola, Joonas Multanen, Joost Hoozemans, Pekka Jääskeläinen:
AEx: Automated High-Level Synthesis of Compiler Programmable Co-Processors. J. Signal Process. Syst. 95(9): 1051-1065 (2023)
[c81]
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Panagiotis Mousouliotis, Topi Leppänen, Pekka Jääskeläinen, Nikos Petrellis, Panagiotis Christakos, Georgios Keramidas, Christos P. Antonopoulos, Nikolaos S. Voros:
On the OpenCL Support for Streaming Fixed-Function Accelerators on Embedded SoC FPGAs. ARC 2023: 51-65
[c80]
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Maarten J. Molendijk, Floran A. M. de Putter, Manil Dev Gomony, Pekka Jääskeläinen, Henk Corporaal:
BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport-Triggered NN SoC. ICCD 2023: 78-85
[c79]
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Jan Solanti, Topi Leppänen, Pekka Jääskeläinen:
Open Standard Software Stack for Low Latency Offloading from Lightweight Devices to Remote Heterogeneous Platforms. IWOCL 2023: 25:1
[c78]
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Topi Leppänen, Joonas Multanen, Leevi Leppänen, Pekka Jääskeläinen:
AFOCL: Portable OpenCL Programming of FPGAs via Automated Built-in Kernel Management. NorCAS 2023: 1-7
[i5]
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  - journals/corr/abs-2305-04804
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Erfan Momeni Yazdi, Markku J. Mäkitalo, Julius Ikkala, Pekka Jääskeläinen:
TauBench 1.1: A Dynamic Benchmark for Graphics Rendering. CoRR abs/2305.04804 (2023)
[i4]
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  - journals/corr/abs-2309-00407
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Jan Solanti, Michal Babej, Julius Ikkala, Pekka Jääskeläinen:
PoCL-R: An Open Standard Based Offloading Layer for Heterogeneous Multi-Access Edge Computing with Server Side Scalability. CoRR abs/2309.00407 (2023)
2022
[j28]
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Petrus E. J. Kivi, Markku J. Mäkitalo, Jakub Zádník, Julius Ikkala, Vinod Kumar Malamal Vadakital, Pekka Jääskeläinen:
Real-Time Rendering of Point Clouds With Photorealistic Effects: A Survey. IEEE Access 10: 13151-13173 (2022)
[j27]
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Jakub Zádník, Markku J. Mäkitalo, Jarno Vanne, Pekka Jääskeläinen:
Image and Video Coding Techniques for Ultra-low Latency. ACM Comput. Surv. 54(11s): 231:1-231:35 (2022)
[j26]
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Topi Leppänen, Atro Lotvonen, Pekka Jääskeläinen:
Cross-vendor programming abstraction for diverse heterogeneous platforms. Frontiers Comput. Sci. 4 (2022)
[j25]
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Joonas Multanen, Kari Hepola, Asif Ali Khan, Jerónimo Castrillón, Pekka Jääskeläinen:
Energy-Efficient Instruction Delivery in Embedded Systems With Domain Wall Memory. IEEE Trans. Computers 71(9): 2010-2021 (2022)
[c77]
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Kari Hepola, Joonas Multanen, Pekka Jääskeläinen:
Dual-IS: Instruction Set Modality for Efficient Instruction Level Parallelism. ARCS 2022: 17-32
[c76]
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Kari Hepola, Joonas Multanen, Pekka Jääskeläinen:
OpenASIP 2.0: Co-Design Toolset for RISC-V Application-Specific Instruction-Set Processors. ASAP 2022: 161-165
[c75]
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Markku J. Mäkitalo, Erwan Leria, Julius Ikkala, Pekka Jääskeläinen:
Real-Time Light Field Path Tracing. CGI 2022: 211-226
[c74]
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Kanishkan Vadivel, Barry de Bruin, Roel Jordans, Henk Corporaal, Pekka Jääskeläinen:
Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures. DSD 2022: 157-164
[c73]
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Joel Alanko, Markku J. Mäkitalo, Pekka Jääskeläinen:
TauBench: Dynamic Benchmark for Graphics Rendering. VISIGRAPP (1: GRAPP) 2022: 172-179
[c72]
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Jakub Zádník, Markku J. Mäkitalo, Pekka Jääskeläinen:
Pruned Lightweight Encoders for Computer Vision. MMSP 2022: 1-6
[c71]
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  - conf/siggrapha/IkkalaMLLJ22
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Julius Ikkala, Markku J. Mäkitalo, Tuomas Lauttia, Erwan Leria, Pekka Jääskeläinen:
Tauray: A Scalable Real-Time Open-Source Path Tracer for Stereo and Light Field Displays. SIGGRAPH Asia Technical Communications 2022: 11:1-11:4
[i3]
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  - journals/corr/abs-2211-11331
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Maarten Molendijk, Floran de Putter, Manil Dev Gomony, Pekka Jääskeläinen, Henk Corporaal:
BrainTTA: A 35 fJ/op Compiler Programmable Mixed-Precision Transport-Triggered NN SoC. CoRR abs/2211.11331 (2022)
[i2]
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  - journals/corr/abs-2211-13137
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Jakub Zádník, Markku J. Mäkitalo, Pekka Jääskeläinen:
Pruned Lightweight Encoders for Computer Vision. CoRR abs/2211.13137 (2022)
2021
[j24]
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Sven Gesper, Moritz Weißbrich, Tobias Stuckenberg, Pekka Jääskeläinen, Holger Blume, Guillermo Payá Vayá:
Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments. Int. J. Parallel Program. 49(4): 541-569 (2021)
[j23]
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Carlo Sau, Claudia Rinaldi, Luigi Pomante, Francesca Palumbo, Giacomo Valente, Tiziana Fanni, Marcos Martinez de Alejandro, Frank van der Linden, Twan Basten, Marc Geilen, Geran Peeren, Jirí Kadlec, Pekka Jääskeläinen, Lubomír Bulej, Francisco Barranco, Jukka Saarinen, Tero Säntti, Maria Katiuscia Zedda, Victor Sanchez, Shayan Tabatabaei Nikkhah, Dip Goswami, Guillermo Amat, Lukás Marsík, Mark van Helvoort, Luis Medina, Zaid Al-Ars, Ad de Beer:
Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project. Microprocess. Microsystems 87: 104350 (2021)
[c70]
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Julius Ikkala, Petrus E. J. Kivi, Joel Alanko, Markku J. Mäkitalo, Pekka Jääskeläinen:
DDISH-GI: Dynamic Distributed Spherical Harmonics Global Illumination. CGI 2021: 433-451
[c69]
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Jakub Zádník, Markku J. Mäkitalo, Jussi Iho, Pekka Jääskeläinen:
Performance of Texture Compression Algorithms in Low-Latency Computer Vision Tasks. EUVIP 2021: 1-6
[c68]
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Joost Hoozemans, Kati Tervo, Pekka Jääskeläinen, Zaid Al-Ars:
Energy Efficient Multistandard Decompressor ASIP. ICCDE 2021: 14-19
[c67]
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Topi Leppänen, Panagiotis Mousouliotis, Georgios Keramidas, Joonas Multanen, Pekka Jääskeläinen:
Unified OpenCL Integration Methodology for FPGA Designs. NorCAS 2021: 1-7
[c66]
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Jan Solanti, Michal Babej, Julius Ikkala, Vinod Kumar Malamal Vadakital, Pekka Jääskeläinen:
PoCL-R: A Scalable Low Latency Distributed OpenCL Runtime. SAMOS 2021: 78-94
2020
[j22]
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Markku J. Mäkitalo, Petrus E. J. Kivi, Pekka Jääskeläinen:
Systematic Evaluation of the Quality Benefits of Spatiotemporal Sample Reprojection in Real-Time Stereoscopic Path Tracing. IEEE Access 8: 133514-133526 (2020)
[j21]
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Joonas Multanen, Heikki Kultala, Kati Tervo, Pekka Jääskeläinen:
Energy Efficient Low Latency Multi-issue Cores for Intelligent Always-On IoT Applications. J. Signal Process. Syst. 92(10): 1057-1073 (2020)
[c65]
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Luigi Pomante, Francesca Palumbo, Claudia Rinaldi, Giacomo Valente, Carlo Sau, Tiziana Fanni, Frank van der Linden, Twan Basten, Marc Geilen, Geran Peeren, Jirí Kadlec, Pekka Jääskeläinen, Marcos Martinez de Alejandro, Jukka Saarinen, Tero Säntti, Maria Katiuscia Zedda, Victor Sanchez, Dip Goswami, Zaid Al-Ars, Ad de Beer:
Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project. DSD 2020: 378-385
[c64]
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Kati Tervo, Samawat Malik, Topi Leppänen, Pekka Jääskeläinen:
TTA-SIMD Soft Core Processors. FPL 2020: 79-84
[c63]
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Atro Lotvonen, Matias Koskela, Pekka Jääskeläinen:
Machine Learning is the Solution Also for Foveated Path Tracing Reconstruction. VISIGRAPP (1: GRAPP) 2020: 361-367
[c62]
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Joonas Multanen, Kari Hepola, Pekka Jääskeläinen:
Programmable Dictionary Code Compression for Instruction Stream Energy Efficiency. ICCD 2020: 356-363
[c61]
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Georgios Keramidas, Christos P. Antonopoulos, Nikolaos S. Voros, Pekka Jääskeläinen, Marisa Catalán Cid, Evangelia I. Zacharaki, Apostolos P. Fournaris, Aris S. Lalos:
CPSoSaware: Cross-Layer Cognitive Optimization Tools & Methods for the Lifecycle Support of Dependable CPSoS. ISVLSI 2020: 470-475
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Michal Babej, Pekka Jääskeläinen:
HIPCL: Tool for Porting CUDA Applications to Advanced OpenCL Platforms Through HIP. IWOCL 2020: 18:1-18:3
[c59]
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Jan Solanti, Michal Babej, Julius Ikkala, Pekka Jääskeläinen:
POCL-R: Distributed OpenCL Runtime for Low Latency Remote Offloading. IWOCL 2020: 19:1-19:2
[c58]
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Ali BanaGozar, Kanishkan Vadivel, Joonas Multanen, Pekka Jääskeläinen, Sander Stuijk, Henk Corporaal:
System Simulation of Memristor Based Computation in Memory Platforms. SAMOS 2020: 152-168

2010 – 2019

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2019
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Carlos S. de La Lama, Pekka Jääskeläinen, Heikki Kultala, Jarmo Takala:
Programmable and Scalable Architecture for Graphics Processing Units. Trans. High Perform. Embed. Archit. Compil. 5: 21-38 (2019)
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Matias Koskela, Kalle Immonen, Markku J. Mäkitalo, Alessandro Foi, Timo Viitanen, Pekka Jääskeläinen, Heikki Kultala, Jarmo Takala:
Blockwise Multi-Order Feature Regression for Real-Time Path-Tracing Reconstruction. ACM Trans. Graph. 38(5): 138:1-138:14 (2019)
[j18]
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Heikki Kultala, Timo Viitanen, Heikki Berg, Pekka Jääskeläinen, Joonas Multanen, Mikko Kokkonen, Kalle Raiskila, Tommi Zetterman, Jarmo Takala:
LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor. IEEE Trans. Very Large Scale Integr. Syst. 27(5): 1029-1042 (2019)
[j17]
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Zaid Al-Ars, Steven van der Vlugt, Pekka Jääskeläinen, Frank van der Linden:
ALMARVI System Solution for Image and Video Processing in Healthcare, Surveillance and Mobile Applications. J. Signal Process. Syst. 91(1): 1-7 (2019)
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Pekka Jääskeläinen, Ville Korhonen, Matias Koskela, Jarmo Takala, Karen O. Egiazarian, Aram Danielyan, Cristóvão Cruz, James Price, Simon McIntosh-Smith:
Exploiting Task Parallelism with OpenCL: A Case Study. J. Signal Process. Syst. 91(1): 33-46 (2019)
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Zaid Al-Ars, Twan Basten, Ad de Beer, Marc Geilen, Dip Goswami, Pekka Jääskeläinen, Jirí Kadlec, Marcos Martinez de Alejandro, Francesca Palumbo, Geran Peeren, Luigi Pomante, Frank van der Linden, Jukka Saarinen, Tero Säntti, Carlo Sau, Maria Katiuscia Zedda:
The FitOptiVis ECSEL project: highly efficient distributed embedded image/video processing in cyber-physical systems. CF 2019: 333-338
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Alex Hirvonen, Kati Tervo, Heikki Kultala, Pekka Jääskeläinen:
AEx: Automated Customization of Exposed Datapath Soft-Cores. DSD 2019: 35-42
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Markku J. Mäkitalo, Petrus E. J. Kivi, Matias Koskela, Pekka Jääskeläinen:
Reducing Computational Complexity of Real-Time Stereoscopic Ray Tracing with Spatiotemporal Sample Reprojection. VISIGRAPP (1: GRAPP) 2019: 367-374
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Joonas Multanen, Pekka Jääskeläinen, Asif Ali Khan, Fazal Hameed, Jerónimo Castrillón:
SHRIMP: Efficient Instruction Delivery with Domain Wall Memory. ISLPED 2019: 1-6
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Matias Koskela, Atro Lotvonen, Markku J. Mäkitalo, Petrus E. J. Kivi, Timo Viitanen, Pekka Jääskeläinen:
Foveated Real-Time Path Tracing in Visual-Polar Space. EGSR (DL/I) 2019: 39-50
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Sven Gesper, Moritz Weißbrich, Stephan Nolting, Tobias Stuckenberg, Pekka Jääskeläinen, Holger Blume, Guillermo Payá Vayá:
Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments. SAMOS 2019: 3-17
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Kanishkan Vadivel, Roel Jordans, Sander Stuijk, Henk Corporaal, Pekka Jääskeläinen, Heikki Kultala:
Towards Efficient Code Generation for Exposed Datapath Architectures. SCOPES 2019: 86-89
2018
[j15]
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Matias Koskela, Kalle Immonen, Timo Viitanen, Pekka Jääskeläinen, Joonas Multanen, Jarmo H. Takala:
Instantaneous foveated preview for progressive Monte Carlo rendering. Comput. Vis. Media 4(3): 267-276 (2018)
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Timo Viitanen, Janne Helkala, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Tommi Zetterman, Heikki Berg:
Variable Length Instruction Compression on Transport Triggered Architectures. Int. J. Parallel Program. 46(6): 1283-1303 (2018)
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Timo Viitanen, Matias Koskela, Pekka Jääskeläinen, Aleksi Tervo, Jarmo Takala:
PLOCTree: A Fast, High-Quality Hardware BVH Builder. Proc. ACM Comput. Graph. Interact. Tech. 1(2): 35:1-35:19 (2018)
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Mona Aghababaeetafreshi, Dani Korpi, Matias Koskela, Pekka Jääskeläinen, Mikko Valkama, Jarmo Takala:
Software Defined Radio Implementation of a Digital Self-interference Cancellation Method for Inband Full-Duplex Radio Using Mobile Processors. J. Signal Process. Syst. 90(10): 1297-1309 (2018)
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Joonas Multanen, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala:
Instruction Fetch Energy Reduction with Biased SRAMs. J. Signal Process. Syst. 90(11): 1519-1532 (2018)
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Timo Viitanen, Matias Koskela, Kalle Immonen, Markku J. Mäkitalo, Pekka Jääskeläinen, Jarmo Takala:
Sparse Sampling for Real-time Ray Tracing. VISIGRAPP (1: GRAPP) 2018: 295-302
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Pekka Jääskeläinen, Aleksi Tervo, Guillermo Payá Vayá, Timo Viitanen, Nicolai Behmann, Jarmo Takala, Holger Blume:
Transport-Triggered Soft Cores. IPDPS Workshops 2018: 83-90
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Mathieu Léonardon, Camille Leroux, Pekka Jääskeläinen, Christophe Jégo, Yvon Savaria:
Transport Triggered Polar Decoders. ISTC 2018: 1-5
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Joonas Multanen, Heikki Kultala, Pekka Jääskeläinen:
Energy-Delay Trade-Offs in Instruction Register File Design. NORCAS 2018: 1-7
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Jos IJzerman, Timo Viitanen, Pekka Jääskeläinen, Heikki Kultala, Lasse Lehtonen, Maurice Peemen, Henk Corporaal, Jarmo Takala:
AivoTTA: an energy efficient programmable accelerator for CNN-based object recognition. SAMOS 2018: 28-37
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Joonas Multanen, Heikki Kultala, Pekka Jääskeläinen, Timo Viitanen, Aleksi Tervo, Jarmo Takala:
LoTTA: Energy-Efficient Processor for Always-On Applications. SiPS 2018: 193-198
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Pekka Jääskeläinen, John Glossner, Martin Jambor, Aleksi Tervo, Matti Rintala:
Offloading C++17 Parallel STL on System Shared Virtual Memory Platforms. ISC Workshops 2018: 637-647
2017
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Timo Viitanen, Matias Koskela, Pekka Jääskeläinen, Kalle Immonen, Jarmo Takala:
Fast Hardware Construction and Refitting of Quantized Bounding Volume Hierarchies. Comput. Graph. Forum 36(4): 167-178 (2017)
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Timo Viitanen, Matias Koskela, Pekka Jääskeläinen, Heikki Kultala, Jarmo Takala:
MergeTree: A Fast Hardware HLBVH Constructor for Animated Ray Tracing. ACM Trans. Graph. 36(5): 169:1-169:14 (2017)
[c43]
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Heikki O. Kultala, Pekka Jääskeläinen, Johannes IJzerman, Lasse Lehtonen, Timo Viitanen, Markku J. Mäkitalo, Jarmo H. Takala:
Exposed datapath optimizations for loop scheduling. SAMOS 2017: 171-178
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Matias Koskela, Kalle Immonen, Timo Viitanen, Pekka Jääskeläinen, Joonas Multanen, Jarmo Takala:
Foveated instant preview for progressive rendering. SIGGRAPH Asia Technical Briefs 2017: 10:1-10:4
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Jarmo Takala, Pekka Jääskeläinen, Teemu Pitkänen:
Codesign Case Study on Transport-Triggered Architectures. Handbook of Hardware/Software Codesign 2017: 1303-1337
2016
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Tomi Äijö, Pekka Jääskeläinen, Tapio Elomaa, Heikki Kultala, Jarmo Takala:
Integer Linear Programming-Based Scheduling for Transport Triggered Architectures. ACM Trans. Archit. Code Optim. 12(4): 59:1-59:22 (2016)
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Heikki Kultala, Timo Viitanen, Pekka Jääskeläinen, Janne Helkala, Jarmo Takala:
Improving Code Density with Variable Length Encoding Aware Instruction Scheduling. J. Signal Process. Syst. 84(3): 435-446 (2016)
[c41]
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Mona Aghababaeetafreshi, Matias Koskela, Dani Korpi, Pekka Jääskeläinen, Mikko Valkama, Jarmo Takala:
Software defined radio implementation of adaptive nonlinear digital self-interference cancellation for mobile inband full-duplex radio. GlobalSIP 2016: 733-737
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Matias Koskela, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala:
Half-precision Floating-point Ray Traversal. VISIGRAPP (1: GRAPP) 2016: 171-178
[c39]
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Nicolai Behmann, Christopher Seifert, Guillermo Payá Vayá, Holger Blume, Pekka Jääskeläinen, Joonas Multanen, Heikki Kultala, Jarmo Takala, Joachim Thiemann, Steven van de Par:
Customized high performance low power processor for binaural speaker localization. ICECS 2016: 392-395
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Matias Koskela, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala:
Foveated Path Tracing - A Literature Review and a Performance Gain Analysis. ISVC (1) 2016: 723-732
[c37]
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Joonas Multanen, Heikki Kultala, Matias Koskela, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala, Aram Danielyan, Cristóvão Cruz:
OpenCL programmable exposed datapath high performance low-power image signal processor. NORCAS 2016: 1-6
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Heikki O. Kultala, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala:
Aggressively bypassing list scheduler for transport triggered architectures. SAMOS 2016: 253-260
[c35]
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Timo Viitanen, Matias Koskela, Pekka Jääskeläinen, Jarmo Takala:
Multi bounding volume hierarchies for ray tracing pipelines. SIGGRAPH Asia Technical Briefs 2016: 8
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Joonas Multanen, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala:
Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies. SiPS 2016: 63-68
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Pekka Jääskeläinen, Carlos Sánchez de La Lama, Erik Schnetter, Kalle Raiskila, Jarmo Takala, Heikki Berg:
pocl: A Performance-Portable OpenCL Implementation. CoRR abs/1611.07083 (2016)
2015
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Pekka Jääskeläinen, Carlos Sánchez de La Lama, Erik Schnetter, Kalle Raiskila, Jarmo Takala, Heikki Berg:
pocl: A Performance-Portable OpenCL Implementation. Int. J. Parallel Program. 43(5): 752-785 (2015)
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Pekka Jääskeläinen, Jani Boutellier:
Data Intensive Computing: From Modeling to Implementation. J. Signal Process. Syst. 80(1): 1-2 (2015)
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Pekka Jääskeläinen, Heikki Kultala, Timo Viitanen, Jarmo Takala:
Code Density and Energy Efficiency of Exposed Datapath Architectures. J. Signal Process. Syst. 80(1): 49-64 (2015)
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Hervé Yviquel, Alexandre Sanchez, Pekka Jääskeläinen, Jarmo Takala, Mickaël Raulet, Emmanuel Casseau:
Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs. J. Signal Process. Syst. 80(1): 121-136 (2015)
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Mona Aghababaee Tafreshi, Juha Yli-Kaakinen, Toni Levanen, Ville Korhonen, Pekka Jääskeläinen, Markku Renfors, Mikko Valkama, Jarmo Takala:
Parallel processing intensive digital front-end for IEEE 802.11ac receiver. ACSSC 2015: 1619-1626
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Ville Korhonen, Pekka Jääskeläinen, Matias Koskela, Timo Viitanen, Jarmo Takala:
Rapid customization of image processors using Halide. GlobalSIP 2015: 629-633
[c31]
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Joonas Multanen, Timo Viitanen, Henry Linjamaki, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Lauri Koskinen, Jesse Simonsson, Heikki Berg, Kalle Raiskila, Tommi Zetterman:
Power optimizations for transport triggered SIMD processors. SAMOS 2015: 303-309
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Timo Viitanen, Matias Koskela, Pekka Jääskeläinen, Heikki Kultala, Jarmo Takala:
MergeTree: a HLBVH constructor for mobile systems. SIGGRAPH Asia Technical Briefs 2015: 12:1-12:4
2014
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Timo Viitanen, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala:
Heuristics for greedy transport triggered architecture interconnect exploration. CASES 2014: 2:1-2:7
[c28]
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Hervé Yviquel, Alexandre Sanchez, Pekka Jääskeläinen, Jarmo Takala, Mickaël Raulet, Emmanuel Casseau:
Efficient software synthesis of dynamic dataflow programs. ICASSP 2014: 4988-4992
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Xie Wen, Xianjun Jiao, Pekka Jääskeläinen, Heikki Kultala, Canfeng Chen, Heikki Berg, Zhisong Bie:
A high throughput LDPC decoder using a mid-range GPU. ICASSP 2014: 7515-7519
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Blaine Rister, Pekka Jääskeläinen, Olli Silvén, Jari Hannuksela, Joseph R. Cavallaro:
Parallel programming of a symmetric transport-triggered architecture with applications in flexible LDPC encoding. ICASSP 2014: 8380-8384
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Jianbin Fang, Henk J. Sips, Pekka Jääskeläinen, Ana Lucia Varbanescu:
Grover: Looking for Performance Improvement by Disabling Local Memory Usage in OpenCL Kernels. ICPP 2014: 162-171
[c24]
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Janne Helkala, Timo Viitanen, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Tommi Zetterman, Heikki Berg:
Variable length instruction compression on Transport Triggered Architectures. ICSAMOS 2014: 149-155
[c23]
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Janne Janhunen, Pekka Jääskeläinen, Jari Hannuksela, Tero Rintaluoma, Aki Kuusela:
Programmable in-loop deblock filter processor for video decoders. SiPS 2014: 109-114
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Heikki Kultala, Timo Viitanen, Pekka Jääskeläinen, Janne Helkala, Jarmo Takala:
Compiler optimizations for code density of variable length instructions. SiPS 2014: 127-132
2013
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Timo Viitanen, Pekka Jääskeläinen, Otto Esko, Jarmo Takala:
Simplified floating-point division and square root. ICASSP 2013: 2707-2711
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Hervé Yviquel, Emmanuel Casseau, Mickaël Raulet, Pekka Jääskeläinen, Jarmo Takala:
Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms. ISPA 2013: 732-737
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Xianjun Jiao, Canfeng Chen, Pekka Jääskeläinen, Vladimír Guzma, Heikki Berg:
A 122Mb/s Turbo decoder using a mid-range GPU. IWCMC 2013: 1090-1094
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Heikki Kultala, Otto Esko, Pekka Jääskeläinen, Vladimír Guzma, Jarmo Takala, Xianjun Jiao, Tommi Zetterman, Heikki Berg:
Turbo decoding on tailored OpenCL processor. IWCMC 2013: 1095-1100
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Tomasz Patyk, David Guevorkian, Teemu Pitkänen, Pekka Jääskeläinen, Jarmo Takala:
Low-power application-specific FFT processor for LTE applications. ICSAMOS 2013: 28-32
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Jani Boutellier, Pekka Jääskeläinen:
Special session on "Exposed data path architectures: Recent advances and applications". ICSAMOS 2013: 279
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Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala:
Inexpensive correctly rounded floating-point division and square root with input scaling. SiPS 2013: 159-164
2012
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Pekka Jääskeläinen:
From Parallel Programs to Customized Parallel Processors. University of Tampere, Finland, 2012
2011
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Tomasz Patyk, Perttu Salmela, Teemu Pitkänen, Pekka Jääskeläinen, Jarmo Takala:
Design Methodology for Offloading Software Executions to FPGA. J. Signal Process. Syst. 65(2): 245-259 (2011)
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Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala:
Operation set customization in retargetable compilers. ACSCC 2011: 761-765
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Pekka Jääskeläinen, Erno Salminen, Otto Esko, Jarmo Takala:
Customizable Datapath Integrated Lock Unit. SoC 2011: 29-33
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Pekka Jääskeläinen, Erno Salminen, Carlos S. de La Lama, Jarmo Takala, José Ignacio Martínez:
TCEMC: A co-design flow for application-specific multicores. ICSAMOS 2011: 85-92
2010
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Otto Esko, Pekka Jääskeläinen, Pablo Huerta, Carlos S. de La Lama, Jarmo Takala, José Ignacio Martínez:
Customized Exposed Datapath Soft-Core Design Flow with Compiler Support. FPL 2010: 217-222
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Pekka Jääskeläinen, Carlos S. de La Lama, Pablo Huerta, Jarmo Takala:
OpenCL-based design methodology for application-specific processors. ICSAMOS 2010: 223-230

2000 – 2009

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What is the meaning of the colors in the publication lists?

2009
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Carlos S. de La Lama, Pekka Jääskeläinen, Jarmo Takala:
Programmable and Scalable Architecture for Graphics Processing Units. SAMOS 2009: 2-11
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Tero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silvén:
Programmable Accelerators for Reconfigurable Video Decoder. SAMOS 2009: 36-47
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Lassi Nurmi, Perttu Salmela, Pertti Kellomäki, Pekka Jääskeläinen, Jarmo Takala:
Reconfigurable video decoder with transform acceleration. SiPS 2009: 081-086
2008
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Pekka Jääskeläinen, Vladimír Guzma, Viljami Korhonen:
Resource conflict detection in simulation of function unit pipelines. J. Syst. Archit. 54(11): 1058-1064 (2008)
[c6]
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Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala, Heikki Kultala, Mikael Lepistö:
Reducing Context Switch Overhead with Compiler-Assisted Threading. EUC (2) 2008: 461-466
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Vladimír Guzma, Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala:
Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic. SAMOS 2008: 23-32
2007
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Jani Boutellier, Pekka Jääskeläinen, Olli Silvén:
Run-Time Scheduled Hardware Acceleration of MPEG-4 Video Decoding. SoC 2007: 1-4
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Pekka Jääskeläinen, Vladimír Guzma, Jarmo Takala:
Resource Conflict Detection in Simulation of Function Unit Pipelines. SAMOS 2007: 233-240
2006
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Perttu Salmela, Risto Mäkinen, Pekka Jääskeläinen, Jarmo Takala:
Loop Scheduling for Transport Triggered Architecture Processors. SoC 2006: 1-4
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Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala:
Software Pipelining Support for Transport Triggered Architecture Processors. SAMOS 2006: 237-247

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