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Fazal Hameed
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2020 – today
- 2024
- [j16]Asif Ali Khan
, Fazal Hameed
Efficient Memory Layout for Pre-Alignment Filtering of Long DNA Reads Using Racetrack Memory. IEEE Comput. Archit. Lett. 23(1): 129-132 (2024) - 2023
- [j15]Fazal Hameed
An energy-efficient cache replacement policy for ultra-dense racetrack memory. J. Syst. Archit. 137: 102837 (2023) - [j14]Christian Hakert
ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees. IEEE Trans. Computers 72(5): 1488-1502 (2023) - [j13]Asif Ali Khan
DownShift: Tuning Shift Reduction With Reliability for Racetrack Memories. IEEE Trans. Computers 72(9): 2585-2599 (2023) - 2022
- [j12]Fazal Hameed
DNA Pre-Alignment Filter Using Processing Near Racetrack Memory. IEEE Comput. Archit. Lett. 21(2): 53-56 (2022) - [j11]Fazal Hameed
BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5288-5298 (2022) - [j10]Fazal Hameed
ALPHA: A Novel Algorithm-Hardware Co-Design for Accelerating DNA Seed Location Filtering. IEEE Trans. Emerg. Top. Comput. 10(3): 1464-1475 (2022) - [i3]Fazal Hameed
DNA Pre-alignment Filter using Processing Near Racetrack Memory. CoRR abs/2205.02046 (2022) - 2021
- [j9]Fazal Hameed
Improving the Performance of Block-based DRAM Caches Via Tag-Data Decoupling. IEEE Trans. Computers 70(11): 1914-1927 (2021) - [c15]Christian Hakert, Asif Ali Khan, Kuan-Hsun Chen
BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack Memory. DAC 2021: 1111-1116 - 2020
- [j8]Robin Bläsing
Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade. Proc. IEEE 108(8): 1303-1321 (2020) - [j7]Asif Ali Khan
ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0. ACM Trans. Archit. Code Optim. 16(4): 56:1-56:23 (2020) - [j6]Asif Ali Khan
Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories. ACM Trans. Embed. Comput. Syst. 19(6): 44:1-44:26 (2020) - [c14]Asif Ali Khan
Generalized Data Placement Strategies for Racetrack Memories. DATE 2020: 1502-1507
2010 – 2019
- 2019
- [j5]Asif Ali Khan
RTSim: A Cycle-Accurate Simulator for Racetrack Memories. IEEE Comput. Archit. Lett. 18(1): 43-46 (2019) - [j4]Fazal Hameed
A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement. IEEE Trans. Very Large Scale Integr. Syst. 27(10): 2375-2386 (2019) - [c13]Joonas Multanen, Pekka Jääskeläinen
SHRIMP: Efficient Instruction Delivery with Domain Wall Memory. ISLPED 2019: 1-6 - [c12]Asif Ali Khan
Optimizing tensor contractions for embedded devices with racetrack memory scratch-pads. LCTES 2019: 5-18 - [i2]Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jerónimo Castrillón:
ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0. CoRR abs/1903.03597 (2019) - [i1]Asif Ali Khan, Andres Goens, Fazal Hameed, Jerónimo Castrillón:
Generalized Data Placement Strategies for Racetrack Memories. CoRR abs/1912.03507 (2019) - 2018
- [j3]Sarath Mohanachandran Nair
VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1396-1407 (2018) - [j2]Fazal Hameed
Performance and Energy-Efficient Design of STT-RAM Last-Level Cache. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1059-1072 (2018) - [c11]Asif Ali Khan, Fazal Hameed
NVMain Extension for Multi-Level Cache Systems. RAPIDO 2018: 7:1-7:6 - 2017
- [c10]Fazal Hameed
Rethinking on-chip DRAM cache for simultaneous performance and energy optimization. DATE 2017: 362-367 - [c9]Fazal Hameed
Efficient STT-RAM last-level-cache architecture to replace DRAM cache. MEMSYS 2017: 141-151 - 2016
- [j1]Fazal Hameed
Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(4): 651-664 (2016) - [c8]Fabian Oboril, Fazal Hameed
Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches. ISLPED 2016: 236-241 - [c7]Fazal Hameed
Architecting STT Last-Level-Cache for performance and energy improvement. ISQED 2016: 319-324 - 2015
- [b1]Fazal Hameed:
DRAM Aware Last-Level-Cache Policies for Multi-core Systems. Karlsruhe Institute of Technology, 2015 - 2014
- [c6]Fazal Hameed
Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture. DAC 2014: 37:1-37:6 - 2013
- [c5]Fazal Hameed
Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies. CASES 2013: 11:1-11:10 - [c4]Fazal Hameed
Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache. CODES+ISSS 2013: 1:1-1:8 - [c3]Fazal Hameed
Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores. DATE 2013: 77-82 - 2012
- [c2]Fazal Hameed
Dynamic cache management in multi-core architectures through run-time adaptation. DATE 2012: 485-490 - 2011
- [c1]Fazal Hameed, Mohammad Abdullah Al Faruque, Jörg Henkel:
Dynamic thermal management in 3D multi-core architecture through run-time adaptation. DATE 2011: 299-304
Coauthor Index
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