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Christophe Jégo
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2020 – today
- 2024
- [i5]Ian Fischer Schilling, Serdar Sahin, Camille Leroux, Antonio Maria Cipriano, Christophe Jégo:
Hardware Implementation of Soft Mapper/Demappers in Iterative EP-based Receivers. CoRR abs/2406.07934 (2024) - 2023
- [j37]Adrien Cassagne
, Romain Tajan, Olivier Aumage, Camille Leroux, Denis Barthou
A DSEL for high throughput and low latency software-defined radio on multicore CPUs. Concurr. Comput. Pract. Exp. 35(23) (2023) - [j36]Bertrand Le Gal
High-performance hard-input LDPC decoding on multi-core devices for optical space links. J. Syst. Archit. 137: 102832 (2023) - [c82]Hugues Almorin, Bertrand Le Gal, Christophe Jégo, Vincent Kissel:
Model Based Design of FMCW Radar Processing Systems on FPGA Platforms. DSD 2023: 24-29 - [c81]Denis Shemonaev, Bertrand Le Gal, Christophe Jégo, Anthony Besseau:
Implementation of an Assignment Algorithm for Object Tracking on a FPGA MPSoC. DSD 2023: 373-380 - [c80]Jonathan Saussereau
Design and Implementation of a RISC-V core with a Flexible Pipeline for Design Space Exploration. ICECS 2023: 1-5 - [c79]Jonathan Saussereau
AsteRISC: A Size-Optimized RISC-V Core for Design Space Exploration. ISCAS 2023: 1-5 - [c78]Malek Ellouze, Romain Tajan, Camille Leroux, Christophe Jégo, Charly Poulliat:
Low-Complexity Algorithm for the Minimum Distance Properties of PAC Codes. ISTC 2023: 1-5 - 2022
- [j35]Ali Haroun, Ali Chamas Al Ghouwayel, Hussein Hijazi, Christophe Jégo:
A novel JFG detection-decoding approach of a vertical shuffle scheduling for iterative MIMO receivers with NB-LDPC codes. Signal Process. 190: 108287 (2022) - [c77]Bertrand Le Gal
High-Performance Gallager-E Decoders for Hard Input LDPC Decoding on Multi-core Devices. DASIP 2022: 3-15 - [c76]Hugues Almorin, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo, Vincent Kissel:
High-throughput FFT architectures using HLS tools. ICECS 2022 2022: 1-4 - [c75]Victor Grimblatt, Guillaume Ferré, Francois Rivet, Christophe Jégo:
An IoT SoC for Agricultural Applications. LASCAS 2022: 1-4 - [c74]Logan Saint-Germain, Bertrand Le Gal, Fabien Baldacci, Jérémie Crenne, Christophe Jégo, Sebastien Loty:
Methodology to Adapt Neural Network on Constrained Device at Topology level. SiPS 2022: 1-6 - [i4]Adrien Cassagne
A DSEL for High Throughput and Low Latency Software-Defined Radio on Multicore CPUs. CoRR abs/2206.06147 (2022) - 2021
- [j34]Victor Grimblatt
How to Feed a Growing Population - An IoT Approach to Crop Health and Growth. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(3): 435-448 (2021) - [c73]Adrien Cassagne
A Flexible and Portable Real-time DVB-S2 Transceiver using Multicore and SIMD CPUs. ISTC 2021: 1-5 - [c72]Malek Ellouze, Camille Leroux, Romain Tajan, Charly Poulliat, Christophe Jégo:
Tailored List Decoding of Polar Codes. ISTC 2021: 1-5 - [c71]Yassine Faize, Jérémie Crenne, Nicolas Hanusse, Christophe Jégo:
An Energy Efficient and Scalable Node Architecture for Sensor Network. NEWCAS 2021: 1-4 - 2020
- [j33]Bertrand Le Gal
Low-latency and high-throughput software turbo decoders on multi-core architectures. Ann. des Télécommunications 75(1-2): 27-42 (2020) - [j32]Yann Delomier, Bertrand Le Gal
Model-based Design of Hardware SC Polar Decoders for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 13(2): 10:1-10:27 (2020) - [j31]Bertrand Le Gal
High-Throughput FFT-SPA Decoder Implementation for Non-Binary LDPC Codes on x86 Multicore Processors. J. Signal Process. Syst. 92(1): 37-53 (2020) - [j30]Yann Delomier, Bertrand Le Gal
Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices. J. Signal Process. Syst. 92(7): 727-745 (2020) - [c70]Vincent Pignoly, Bertrand Le Gal, Christophe Jégo, Benjamin Gadat, Lyonel Barthe:
Fair comparison of hardware and software LDPC decoder implementations for SDR space links. ICECS 2020: 1-4 - [c69]Vincent Pignoly, Bertrand Le Gal, Christophe Jégo, Benjamin Gadat, Lyonel Barthe:
High speed LDPC decoding for optical space link. ICECS 2020: 1-4 - [c68]Bertrand Le Gal, Yann Delomier, Camille Leroux, Christophe Jégo:
Low-Latency Sorter Architecture for Polar Codes Successive-Cancellation-List Decoding. SiPS 2020: 1-5
2010 – 2019
- 2019
- [j29]Adrien Cassagne
AFF3CT: A Fast Forward Error Correction Toolbox! SoftwareX 10: 100345 (2019) - [j28]Mathieu Léonardon
Fast and Flexible Software Polar List Decoders. J. Signal Process. Syst. 91(8): 937-952 (2019) - [c67]Victor Grimblatt, Guillaume Ferré, Francois Rivet, Christophe Jégo, Nicolas Vergara:
Precision Agriculture for Small to Medium Size Farmers - An IoT Approach. ISCAS 2019: 1-5 - [c66]Yann Delomier, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo:
Generation of Efficient Self-adaptive Hardware Polar Decoders Using High-Level Synthesis. SiPS 2019: 242-247 - 2018
- [j27]Bertrand Le Gal
High-performance software implementations of SCAN decoder for polar codes. Ann. des Télécommunications 73(5-6): 401-412 (2018) - [j26]Imen Debbabi
Multicore and Manycore Implementations of ADMM-based Decoders for LDPC Decoding. J. Signal Process. Syst. 90(11): 1551-1567 (2018) - [c65]Hayfa Ben Thameur, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
Hardware design of Euclidean Projection modules for ADMM LDPC decoding. ICECS 2018: 73-76 - [c64]Yann Delomier, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo:
From multicore LDPC decoder implementations to FPGA decoder architectures: a case study. ICECS 2018: 89-92 - [c63]Yann Delomier, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo:
Fast Design of Reliable, Flexible and High-Speed AWGN architectures with High Level Synthesis. ICECS 2018: 661-664 - [c62]Mathieu Léonardon, Camille Leroux, David Binet, J. M. Pierre Langlois, Christophe Jégo, Yvon Savaria:
Custom Low Power Processor for Polar Decoding. ISCAS 2018: 1-5 - [c61]Yann Delomier, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo:
Model-based Design of Efficient LDPC Decoder Architectures. ISTC 2018: 1-5 - [c60]Mathieu Léonardon, Camille Leroux, Pekka Jääskeläinen
Transport Triggered Polar Decoders. ISTC 2018: 1-5 - [c59]Vincent Pignoly, Bertrand Le Gal, Christophe Jégo, Benjamin Gadat:
High data rate and flexible hardware QC-LDPC decoder for satellite optical communications. ISTC 2018: 1-5 - [c58]Adrien Cassagne
MIPP: a Portable C++ SIMD Wrapper and its use for Error Correction Coding in 5G Standard. WPMVP@PPoPP 2018: 2:1-2:8 - [c57]Imen Debbabi, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
ADMM hardware decoder for regular LDPC codes using a NISC-based architecture. WCNC 2018: 1-6 - [c56]Hayfa Ben Thameur, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
Implementation aspects of a pipeline ADMM-based LP decoding of LDPC convolutional codes. WCNC 2018: 1-6 - 2017
- [j25]Guillaume Berhault, Camille Leroux, Christophe Jégo, Dominique Dallet:
Memory Requirement Reduction Method for Successive Cancellation Decoding of Polar Codes. J. Signal Process. Syst. 88(3): 425-438 (2017) - [c55]Hayfa Ben Thameur, Nadia Khouja, Fethi Tlili, Bertrand Le Gal, Christophe Jégo:
An LP-based algorithm for decoding terminated LDPC convolutional codes. IINTEC 2017: 95-100 - [c54]Hayfa Ben Thameur, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
A survey on decoding schedules of LDPC convolutional codes and associated hardware architectures. ISCC 2017: 898-905 - [c53]Alireza Ghaffari, Mathieu Léonardon, Yvon Savaria, Christophe Jégo, Camille Leroux:
Improving performance of SCMA MPA decoders using estimation of conditional probabilities. NEWCAS 2017: 21-24 - [c52]Bertrand Le Gal, Christophe Jégo:
Low-latency software LDPC decoders for x86 multi-core devices. SiPS 2017: 1-6 - [c51]Bertrand Le Gal, Camille Leroux, Christophe Jégo:
Successive cancellation decoder for very long polar codes. SiPS 2017: 1-6 - [c50]Hayfa Ben Thameur, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
Reduced complexity ADMM-based schedules for LP decoding of LDPC convolutional codes. SiPS 2017: 1-6 - [c49]Hayfa Ben Thameur, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
Low complexity ADMM-LP based decoding strategy for LDPC convolutional codes. SoftCOM 2017: 1-5 - [i3]Mathieu Léonardon, Adrien Cassagne, Camille Leroux, Christophe Jégo, Louis-Philippe Hamelin, Yvon Savaria:
Fast and Flexible Software Polar List Decoders. CoRR abs/1710.08314 (2017) - 2016
- [j24]Imen Debbabi
Fast Converging ADMM-Penalized Algorithm for LDPC Decoding. IEEE Commun. Lett. 20(4): 648-651 (2016) - [j23]Ali Haroun, Charbel Abdel Nour
Low-Complexity Soft Detection of QAM Demapper for a MIMO System. IEEE Commun. Lett. 20(4): 732-735 (2016) - [j22]Bertrand Le Gal
High-Throughput Multi-Core LDPC Decoders Based on x86 Processor. IEEE Trans. Parallel Distributed Syst. 27(5): 1373-1386 (2016) - [j21]Thibaud Tonnellier
Lowering the Error Floor of Turbo Codes With CRC Verification. IEEE Wirel. Commun. Lett. 5(4): 404-407 (2016) - [j20]Imen Debbabi
Real Time LP Decoding of LDPC Codes for High Correction Performance Applications. IEEE Wirel. Commun. Lett. 5(6): 676-679 (2016) - [c48]Thibaud Tonnellier
Hardware architecture for lowering the error floor of LTE turbo codes. DASIP 2016: 107-112 - [c47]Imen Debbabi, Nadia Khouja, Fethi Tlili, Bertrand Le Gal, Christophe Jégo:
Multicore implementation of LDPC decoders based on ADMM algorithm. ICASSP 2016: 971-975 - [c46]Bertrand Le Gal, Camille Leroux, Christophe Jégo:
Memory reduction techniques for successive cancellation decoding of polar codes. ICASSP 2016: 986-990 - [c45]Bertrand Le Gal, Camille Leroux, Christophe Jégo:
A scalable 3-phase polar decoder. ISCAS 2016: 417-420 - [c44]Imen Debbabi, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
Comparison of different schedulings for the ADMM based LDPC decoding. ISTC 2016: 51-55 - [c43]Thibaud Tonnellier
Lowering the error floor of double-binary turbo codes: The flip and check algorithm. ISTC 2016: 156-160 - [c42]Imen Debbabi, Nadia Khouja, Fethi Tlili, Bertrand Le Gal, Christophe Jégo:
Evaluation of the hardware complexity of the ADMM approach for LDPC decoding. WCNC 2016: 1-6 - 2015
- [j19]Bertrand Le Gal, Christophe Jégo:
High-Throughput LDPC Decoder on Low-Power Embedded Processors. IEEE Commun. Lett. 19(11): 1861-1864 (2015) - [j18]Bertrand Le Gal
Multi-Gb/s Software Decoding of Polar Codes. IEEE Trans. Signal Process. 63(2): 349-359 (2015) - [c41]Guillaume Berhault, Camille Leroux, Christophe Jégo, Dominique Dallet:
Hardware implementation of a soft cancellation decoder for polar codes. DASIP 2015: 1-8 - [c40]Imen Debbabi, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo:
Analysis of ADMM-LP algorithm for LDPC decoding, a first step to hardware implementation. ICECS 2015: 356-359 - [c39]Guillaume Berhault, Camille Leroux, Christophe Jégo, Dominique Dallet:
Partial sums computation in polar codes decoding. ISCAS 2015: 826-829 - 2014
- [j17]Bertrand Le Gal, Christophe Jégo, Jérémie Crenne:
A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU Devices. IEEE Embed. Syst. Lett. 6(2): 29-32 (2014) - [j16]Bertrand Le Gal, Christophe Jégo:
GPU-like on-chip system for decoding LDPC codes. ACM Trans. Embed. Comput. Syst. 13(4): 95:1-95:19 (2014) - [j15]Bertrand Le Gal, Christophe Jégo, Camille Leroux:
A Flexible NISC-Based LDPC Decoder. IEEE Trans. Signal Process. 62(10): 2469-2479 (2014) - [c38]Ali Haroun, Charbel Abdel Nour
Low-complexity layered BP-based detection and decoding for a NB-LDPC coded MIMO system. ICC 2014: 5107-5112 - [c37]Ali Haroun, Charbel Abdel Nour
Low-complexity LDPC-coded iterative MIMO receiver based on belief propagation algorithm for detection. ISTC 2014: 213-217 - [c36]Bertrand Le Gal, Camille Leroux, Christophe Jégo:
Software polar decoder on an embedded processor. SiPS 2014: 180-185 - [c35]Ali Haroun, Charbel Abdel Nour
Symbol-based BP detection for MIMO systems associated with non-binary LDPC codes. WCNC 2014: 212-217 - 2013
- [j14]Bertrand Le Gal, Christophe Jégo:
Softcore Processor Optimization According to Real-Application Requirements. IEEE Embed. Syst. Lett. 5(1): 4-7 (2013) - [j13]Oscar Sanchez, Christophe Jégo, Michel Jézéquel:
Analysis of the Convergence Process by EXIT Charts for Parallel Implementations of Turbo Decoders. IEEE Commun. Lett. 17(7): 1427-1430 (2013) - [j12]Bertrand Le Gal, Christophe Jégo:
Méthodologie d'optimisation des processeurs embarqués. Une approche favorisant la réduction de la surface et de la consommation des processeurs embarqués. Tech. Sci. Informatiques 32(6): 725-754 (2013) - [c34]Paolo Meloni, Christophe Jégo:
Welcome to the 2013 conference on design and architectures for signal and image processing (DASIP) in Cagliari, Italy. DASIP 2013: 8 - [c33]Yangyang Tang, Emmanuel Boutillon
Muller C-element based Decoder (MCD): A decoder against transient faults. ISCAS 2013: 1680-1683 - [c32]Guillaume Berhault, Camille Leroux, Christophe Jégo, Dominique Dallet:
Partial sums generation architecture for successive cancellation decoding of polar codes. SiPS 2013: 407-412 - [i2]Guillaume Berhault, Camille Leroux, Christophe Jégo, Dominique Dallet:
Partial Sums Generation Architecture for Successive Cancellation Decoding of Polar Codes. CoRR abs/1309.7818 (2013) - [i1]Guillaume Berhault, Camille Leroux, Christophe Jégo, Dominique Dallet:
Partial Sums Computation In Polar Codes Decoding. CoRR abs/1310.1712 (2013) - 2012
- [j11]Haisheng Liu, Christophe Jégo, Emmanuel Boutillon, Michel Jézéquel, Jean-Philippe Diguet:
A contribution to the reduction of the dynamic power dissipation in the turbo decoder. Ann. des Télécommunications 67(7-8): 397-406 (2012) - [j10]Patrick Adde, Daniel Gomez Toro, Christophe Jégo:
Design of an Efficient Maximum Likelihood Soft Decoder for Systematic Short Block Codes. IEEE Trans. Signal Process. 60(7): 3914-3919 (2012) - [c31]Bertrand Le Gal, Christophe Jégo:
FPGA prototyping of an ASIP LDPC decoder for the DVB-T2 standard. DASIP 2012: 1-2 - [c30]Yangyang Tang, Chris Winstead, Emmanuel Boutillon, Christophe Jégo, Michel Jézéquel:
An LDPC decoding method for fault-tolerant digital logic. ISCAS 2012: 3025-3028 - [c29]Chris Winstead, Yangyang Tang, Emmanuel Boutillon, Christophe Jégo, Michel Jézéquel:
A space-time redundancy technique for embedded stochastic error correction. ISTC 2012: 36-40 - [c28]Bertrand Le Gal, Christophe Jégo:
Design of an ASIP LDPC Decoder Compliant with Digital Communication Standards. SiPS 2012: 19-24 - [c27]Oscar Sanchez, Michel Jézéquel, Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy, Christophe Jégo:
A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders. SiPS 2012: 288-293 - 2011
- [j9]Matthieu Arzel, Cyril Lahuec, Christophe Jégo, Warren J. Gross, Yvain Bruned
Stochastic Multiple Stream Decoding of Cortex Codes. IEEE Trans. Signal Process. 59(7): 3486-3491 (2011) - [j8]Camille Leroux, Christophe Jégo, Patrick Adde, Deepak Gupta, Michel Jézéquel:
Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture. J. Signal Process. Syst. 64(1): 17-29 (2011) - [c26]Aurélien Ribon, Bertrand Le Gal, Christophe Jégo, Dominique Dallet:
Assertion support in high-level synthesis design flow. FDL 2011: 1-8 - [c25]Meng Li, Charbel Abdel Nour, Christophe Jégo, Jianxiao Yang, Catherine Douillard
Efficient iterative receiver for bit-Interleaved Coded Modulation according to the DVB-T2 standard. ICASSP 2011: 3168-3171 - [c24]Meng Li, Charbel Abdel Nour
A shuffled iterative bit-interleaved coded modulation receiver for the DVB-T2 standard: Design, implementation and FPGA prototyping. SiPS 2011: 55-60 - [c23]Yangyang Tang, Emmanuel Boutillon, Christophe Jégo, Michel Jézéquel:
Hardware efficiency versus error probability in unreliable computation. SiPS 2011: 168-173 - 2010
- [j7]Quang Trung Dong, Matthieu Arzel
Stochastic Decoding of Turbo Codes. IEEE Trans. Signal Process. 58(12): 6421-6425 (2010) - [c22]Yangyang Tang, Emmanuel Boutillon, Christophe Jégo, Michel Jézéquel:
A new single-error correction scheme based on self-diagnosis residue number arithmetic. DASIP 2010: 27-33 - [c21]Patrick Adde, Christophe Jégo, Raphaël Le Bidan, Jorge Ernesto Pérez Chamorro:
Design and implementation of a soft-decision decoder for Cortex codes. ICECS 2010: 663-666
2000 – 2009
- 2009
- [j6]Christophe Jégo, Warren J. Gross:
Turbo decoding of product codes using adaptive belief propagation. IEEE Trans. Commun. 57(10): 2864-2867 (2009) - [j5]Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel:
High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping. J. Signal Process. Syst. 57(3): 349-361 (2009) - [c20]Christophe Jégo:
FPGA Prototyping Approach for the Validation of Efficient Iterative Decoders in Digital Communication Systems. ERSA 2009: 9-18 - [c19]Rodrigue Imad
Blind Frame Synchronization of Product Codes Based on the Adaptation of the Parity Check Matrix. ICC 2009: 1-5 - [c18]Daoud Karakolah, Christophe Jégo, Charlotte Langlais
Design of an Iterative Receiver for Linearly Precoded MIMO Systems. ISCAS 2009: 597-600 - [c17]Meng Li, Charbel Abdel Nour, Christophe Jégo, Catherine Douillard
Design of rotated QAM mapper/demapper for the DVB-T2 standard. SiPS 2009: 018-023 - 2008
- [j4]Raphaël Le Bidan, Camille Leroux, Christophe Jégo, Patrick Adde, Ramesh Pyndiah:
Reed-Solomon Turbo Product Codes for Optical Communications: From Code Optimization to Decoder Design. EURASIP J. Wirel. Commun. Netw. 2008 (2008) - [j3]Saeed Sharifi Tehrani, Christophe Jégo, Bo Zhu, Warren J. Gross:
Stochastic Decoding of Linear Block Codes With High-Density Parity-Check Matrices. IEEE Trans. Signal Process. 56(11): 5733-5739 (2008) - [c16]Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel:
On the higher efficiency of parallel Reed-Solomon turbo-decoding. ICECS 2008: 1308-1311 - [c15]Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel, Deepak Gupta:
A highly parallel Turbo Product Code decoder without interleaving resource. SiPS 2008: 1-6 - 2007
- [j2]Christophe Jégo, Patrick Adde, Camille Leroux:
Architecture de turbo-décodeur en blocs entièrement parallèle pour la transmission de données au-delà du Gbit/s. Ann. des Télécommunications 62(1-2): 214-239 (2007) - [c14]Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel:
Towards Gb/s turbo decoding of product code onto an FPGA device. ISCAS 2007: 909-912 - [c13]Christophe Jégo, Warren J. Gross:
Turbo Decoding of Product Codes based on the Modified Adaptive Belief Propagation Algorithm. ISIT 2007: 641-644 - [c12]Haisheng Liu, Jean-Philippe Diguet, Christophe Jégo, Michel Jézéquel, Emmanuel Boutillon
Energy Efficient Turbo Decoder with Reduced State Metric Quantization. SiPS 2007: 237-242 - 2006
- [c11]Irene Masinjara Mahafeno, Charlotte Langlais
Reduced Complexity Iterative Multi-User Detector for IDMA (Interleave-Division Multiple Access) System. GLOBECOM 2006 - [c10]Catherine Dezan, Christophe Jégo, Bernard Pottier, Christophe Gouyen, Loïc Lagadec
The Case Study of Block Turbo Decoders on a Framework for Portable Synthesis on FPGA. HICSS 2006 - [c9]Erwan Piriou, Christophe Jégo, Patrick Adde, Raphaël Le Bidan, Michel Jézéquel:
Efficient architecture for Reed Solomon block turbo code. ISCAS 2006 - [c8]Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel:
A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes. ISVLSI 2006: 430-431 - [c7]Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel:
Design, Implementation and Prototyping of a Flexible Architecture Dedicated to Block Turbo Decoding. ReCoSoC 2006: 152-159 - 2005
- [c6]Nabil Abdelli, Pierre Bomel, Emmanuel Casseau, Anne-Marie Fouilliart, Christophe Jégo, Philippe Kajfasz, Bertrand Le Gal, Nathalie Le Heno:
Hardware Virtual Components Compliant with Communication System Standards. DSD 2005: 88-95 - [c5]Caaliph Andriamisaina, Catherine Dezan, Christophe Jégo, Bernard Pottier:
Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit. ERSA 2005: 263-266 - [c4]Emmanuel Casseau, Bertrand Le Gal, Pierre Bomel, Christophe Jégo, Sylvain Huet, Eric Martin:
C-based rapid prototyping for digital signal processing. EUSIPCO 2005: 1-4 - 2004
- [j1]Emmanuel Casseau, Christophe Jégo, Eric Martin:
Synthèse architecturale d'applications temps réel pour technologies submicroniques. Tech. Sci. Informatiques 23(1): 35-66 (2004) - [c3]Emmanuel Casseau, Bertrand Le Gal, Christophe Jégo, Nathalie Le Heno, Eric Martin:
Reed-Solomon behavioral virtual component for communication systems. ISCAS (4) 2004: 173-176 - 2001
- [c2]Emmanuel Casseau, Christophe Jégo, Eric Martin:
Architectural synthesis of digital signal processing applications dedicated to submicron technologies. ICECS 2001: 535-538
1990 – 1999
- 1999
- [c1]Christophe Jégo, Emmanuel Casseau, Eric Martin:
Architectural Synthesis with Interconnection Cost Control. VLSI 1999: 509-520
Coauthor Index
[j36] [c82] [c81] [c77] [c76] [c74] [j33] [j32] [j31] [j30] [c70] [c69] [c68] [j29] [c66] [j27] [j26] [c65] [c64] [c63] [c61] [c59] [c57] [c56] [c55] [c54] [c52] [c51] [c50] [c49] [j24] [j22] [j21] [j20] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [j19] [j18] [c40] [j17] [j16] [j15] [c36] [j14] [j12] [c31] [c28] [c26] [c6] [c4] [c3]
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