research-article

Heuristics for greedy transport triggered architecture interconnect exploration

Authors:

Heikki Kultala,

Pekka Jääskeläinen,

Jarmo TakalaAuthors Info & Claims

CASES '14: Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

Article No.: 2, Pages 1 - 7

https://doi.org/10.1145/2656106.2656123

Published: 12 October 2014 Publication History

Abstract

Most power dissipation in Very Large Instruction Word (VLIW) processors occurs in their large, multi-port register files. Transport Triggered Architecture (TTA) is a VLIW variant whose exposed datapath reduces the need for RF accesses and ports. However, the comparative advantage of TTAs suffers in practice from a wide instruction word and complex interconnection network (IC). We argue that these issues are at least partly due to suboptimal design choices. The design space of possible TTA architectures is very large, and previous automated and ad-hoc design methods often produce inefficient architectures. We propose a reduced design space where efficient TTAs can be generated in a short time using excecution trace-driven greedy exploration. The proposed approach is evaluated by optimizing the equivalent of a 4-issue VLIW architecture. The algorithm finishes quickly and produces a processor with 10% reduced core energy product compared to a fully-connected TTA. Since the generated processor has low IC power and a shorter instruction word than a typical 4-issue VLIW, the results support the hypothesis that these drawbacks of TTA can be worked around with efficient IC design.

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Cited By

Hirvonen ALeppänen THepola KMultanen JHoozemans JJääskeläinen P(2023)AEx: Automated High-Level Synthesis of Compiler Programmable Co-ProcessorsJournal of Signal Processing Systems10.1007/s11265-023-01841-395:9(1051-1065)Online publication date: 15-Feb-2023
https://doi.org/10.1007/s11265-023-01841-3
Kultala HViitanen TBerg HJaaskelainen PMultanen JKokkonen MRaiskila KZetterman TTakala J(2019)LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio CoprocessorIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.289750827:5(1029-1042)Online publication date: May-2019
https://doi.org/10.1109/TVLSI.2019.2897508
Hirvonen ATervo KKultala HJaaskelainen P(2019)AEx: Automated Customization of Exposed Datapath Soft-Cores2019 22nd Euromicro Conference on Digital System Design (DSD)10.1109/DSD.2019.00016(35-42)Online publication date: Aug-2019
https://doi.org/10.1109/DSD.2019.00016
Show More Cited By

Index Terms

Heuristics for greedy transport triggered architecture interconnect exploration
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems

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Published In

cover image ACM Conferences

CASES '14: Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

October 2014

241 pages

ISBN:9781450330503

DOI:10.1145/2656106

General Chairs:
Karam S. Chatha
Qualcomm Research
,
Rolf Ernst
TU Braunschweig, Germany
,
Program Chairs:
Anand Raghunathan
Purdue University
,
Ravishankar Iyer
Intel

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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SIGBED: ACM Special Interest Group on Embedded Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE CAS
IEEE Council on Electronic Design Automation (CEDA)
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 12 October 2014

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Funding Sources

Suomen Akatemia
ARTEMIS joint undertaking
Tekes

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ESWEEK'14

Sponsor:

ESWEEK'14: TENTH EMBEDDED SYSTEM WEEK

October 12 - 17, 2014

New Delhi, India

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Overall Acceptance Rate 52 of 230 submissions, 23%

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Cited By

Hirvonen ALeppänen THepola KMultanen JHoozemans JJääskeläinen P(2023)AEx: Automated High-Level Synthesis of Compiler Programmable Co-ProcessorsJournal of Signal Processing Systems10.1007/s11265-023-01841-395:9(1051-1065)Online publication date: 15-Feb-2023
https://doi.org/10.1007/s11265-023-01841-3
Kultala HViitanen TBerg HJaaskelainen PMultanen JKokkonen MRaiskila KZetterman TTakala J(2019)LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio CoprocessorIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.289750827:5(1029-1042)Online publication date: May-2019
https://doi.org/10.1109/TVLSI.2019.2897508
Hirvonen ATervo KKultala HJaaskelainen P(2019)AEx: Automated Customization of Exposed Datapath Soft-Cores2019 22nd Euromicro Conference on Digital System Design (DSD)10.1109/DSD.2019.00016(35-42)Online publication date: Aug-2019
https://doi.org/10.1109/DSD.2019.00016
Hoozemans JStraten JViitanen TTervo AKadlec JAl-Ars Z(2019)ALMARVI Execution PlatformJournal of Signal Processing Systems10.1007/s11265-018-1424-191:1(61-73)Online publication date: 1-Jan-2019
https://dl.acm.org/doi/10.1007/s11265-018-1424-1
Jaaskelainen PTervo APaya Vaya GViitanen TBehmann NTakala JBlume H(2018)Transport-Triggered Soft Cores2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW.2018.00022(83-90)Online publication date: May-2018
https://doi.org/10.1109/IPDPSW.2018.00022
Kultala HViitanen TJääskeläinen PHelkala JTakala J(2018)Improving Code Density with Variable Length Encoding Aware Instruction SchedulingJournal of Signal Processing Systems10.1007/s11265-015-1081-684:3(435-446)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1007/s11265-015-1081-6
Viitanen THelkala JKultala HJääskeläinen PTakala JZetterman TBerg H(2018)Variable Length Instruction Compression on Transport Triggered ArchitecturesInternational Journal of Parallel Programming10.1007/s10766-018-0568-846:6(1283-1303)Online publication date: 1-Dec-2018
https://dl.acm.org/doi/10.1007/s10766-018-0568-8
Takala JJääskeläinen PPitkänen T(2017)Codesign Case Study on Transport-Triggered ArchitecturesHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_39(1303-1337)Online publication date: 27-Sep-2017
https://doi.org/10.1007/978-94-017-7267-9_39
Multanen JKultala HKoskela MViitanen TJaaskelainen PTakala JDanielyan ACruz C(2016)OpenCL programmable exposed datapath high performance low-power image signal processor2016 IEEE Nordic Circuits and Systems Conference (NORCAS)10.1109/NORCHIP.2016.7792906(1-6)Online publication date: Nov-2016
https://doi.org/10.1109/NORCHIP.2016.7792906
Jääskeläinen PViitanen TTakala JBerg H(2016)HW/SW Co-design Toolset for Customization of Exposed Datapath ProcessorsComputing Platforms for Software-Defined Radio10.1007/978-3-319-49679-5_8(147-164)Online publication date: 30-Dec-2016
https://doi.org/10.1007/978-3-319-49679-5_8
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