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Computer Science > Hardware Architecture

arXiv:2211.11331 (cs)
[Submitted on 21 Nov 2022]

Title:BrainTTA: A 35 fJ/op Compiler Programmable Mixed-Precision Transport-Triggered NN SoC

Authors:Maarten Molendijk, Floran de Putter, Manil Gomony, Pekka Jääskeläinen, Henk Corporaal
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Abstract:Recently, accelerators for extremely quantized deep neural network (DNN) inference with operand widths as low as 1-bit have gained popularity due to their ability to largely cut down energy cost per inference. In this paper, a flexible SoC with mixed-precision support is presented. Contrary to the current trend of fixed-datapath accelerators, this architecture makes use of a flexible datapath based on a Transport-Triggered Architecture (TTA). The architecture is fully programmable using C. The accelerator has a peak energy efficiency of 35/67/405 fJ/op (binary, ternary, and 8-bit precision) and a throughput of 614/307/77 GOPS, which is unprecedented for a programmable architecture.
Subjects: Hardware Architecture (cs.AR)
Cite as: arXiv:2211.11331 [cs.AR]
  (or arXiv:2211.11331v1 [cs.AR] for this version)
  https://doi.org/10.48550/arXiv.2211.11331

Submission history

From: Floran de Putter [view email]
[v1] Mon, 21 Nov 2022 10:33:13 UTC (1,888 KB)
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