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Jiun-Lang Huang
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2020 – today
- 2024
- [c60]Ching-Hsuan Liu, Chih-Ming Chen, Jing-Kai Lou, Ming-Feng Tsai, Jiun-Lang Huang, Chuan-Ju Wang:
SARA: Semantic-assisted Reinforced Active Learning for Entity Alignment. IJCNN 2024: 1-10 - 2023
- [c59]Hao Cheng, Chi-Jhe Li, Hung-Lin Chen, Jiun-Lang Huang:
BDD-Based Self-Test Program Generation for Processor Cores. ITC-Asia 2023: 1-6 - 2022
- [c58]Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Charlie Chung-Ping Chen:
Intelligent Design Automation for Heterogeneous Integration. ISPD 2022: 105-106 - [c57]Jia-Ruei Liang, Ya-Ni Hsieh, Jiun-Lang Huang:
Test Response Compaction for Software-Based Self-Test. ITC-Asia 2022: 49-54 - 2021
- [c56]Kai-Hsun Chen, Bo-Yi Yang, Jia-Ruei Liang, Hung-Lin Chen, Jiun-Lang Huang:
Automatic Test Program Generation for Transition Delay Faults in Pipelined Processors. ITC-Asia 2021: 1-6 - [c55]Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen:
Opportunities for 2.5/3D Heterogeneous SoC Integration. VLSI-DAT 2021: 1 - 2020
- [c54]Ching-Yuan Chen, Ching-Hong Cheng, Jiun-Lang Huang, Krishnendu Chakrabarty
:
Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model. ETS 2020: 1-6 - [c53]Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen:
Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. ICCAD 2020: 125:1-125:7 - [c52]Kuen-Wei Yeh, Jiun-Lang Huang:
DSSP-ATPG: A Deterministic Search-Space Parallel Test Pattern Generator. ITC-Asia 2020: 124-129
2010 – 2019
- 2019
- [c51]Ching-Yuan Chen, Jiun-Lang Huang:
Reinforcement-Learning-Based Test Program Generation for Software-Based Self-Test. ATS 2019: 73-78 - [c50]Kai-Hsun Chen, Ching-Yuan Chen, Jiun-Lang Huang:
Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime. DDECS 2019: 1-2 - [c49]Wei-Chen Huang, Guan-Hao Hou, Jiun-Lang Huang, Terry Kuo:
An FPGA-Based Data Receiver for Digital IC Testing. ITC-Asia 2019: 25-30 - 2018
- [j19]Jin-Fu Li
Conference Reports: Report on 2017 IEEE Asian Test Symposium. IEEE Des. Test 35(2): 103-104 (2018) - [c48]Guan-Hao Hou, Wei-Chen Huang, Jiun-Lang Huang, Terry Kuo:
Design and Implementation of an FPGA-Based 16-Channel Data/Timing Formatter. ATS 2018: 209-214 - [c47]Bo-Yi Li, Jiun-Lang Huang:
A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction. ISOCC 2018: 9-10 - 2017
- [c46]Yang-Kai Huang, Kuan-Te Li, Chih-Lung Hsiao, Chia-An Lee, Jiun-Lang Huang, Terry Kuo:
Design and Implementation of an EG-Pool Based FPGA Formatter with Temperature Compensation. ATS 2017: 88-93 - [c45]Tsung-Yen Tsai, Jiun-Lang Huang:
Source code transformation for software-based on-line error detection. DSC 2017: 305-309 - 2016
- [j18]Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang:
CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator. J. Electron. Test. 32(5): 625-638 (2016) - [c44]Po-Fan Hou, Yi-Tsung Lin, Jiun-Lang Huang, Ann Shih, Zoe F. Conroy:
An IR-Drop Aware Test Pattern Generator for Scan-Based At-Speed Testing. ATS 2016: 167-172 - 2015
- [j17]Yu-Yi Chen, Jiun-Lang Huang, Terry Kuo, Xuan-Lun Huang:
Design and Implementation of an FPGA-Based Data/Timing Formatter. J. Electron. Test. 31(5-6): 549-559 (2015) - [j16]Tsung-Ching Jim Huang, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng
Design, Automation, and Test for Low-Power and Reliable Flexible Electronics. Found. Trends Electron. Des. Autom. 9(2): 99-210 (2015) - [c43]Chun-Hao Chang, Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang:
SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator. ATS 2015: 43-48 - [c42]Guo-Yu Lin, Kun-Han Tsai, Jiun-Lang Huang, Wu-Tung Cheng:
A test-application-count based learning technique for test time reduction. VLSI-DAT 2015: 1-4 - 2014
- [c41]Chung-Yun Wang, Yu-Yi Chen, Jiun-Lang Huang, Xuan-Lun Huang:
FPGA-Based Subset Sum Delay Lines. ATS 2014: 287-291 - 2013
- [j15]Shyue-Kung Lu, Huan-Hua Huang, Jiun-Lang Huang, Pony Ning:
Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 165-169 (2013) - [j14]Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting Cheng
Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 465-474 (2013) - [c40]Shyue-Kung Lu, Hao-Cheng Jheng, Masaki Hashizume, Jiun-Lang Huang, Pony Ning:
Fault Scrambling Techniques for Yield Enhancement of Embedded Memories. Asian Test Symposium 2013: 215-220 - [c39]H.-J. Lin, Xuan-Lun Huang, Jiun-Lang Huang:
A mutual characterization based SAR ADC self-testing technique. ETS 2013: 1-6 - [c38]S.-S. Lin, C.-L. Kao, Jiun-Lang Huang, C.-C. Lee, Xuan-Lun Huang:
An IDDQ-based source driver IC design-for-test technique. ICCAD 2013: 393-398 - [c37]Kuen-Wei Yeh, Jiun-Lang Huang, Hao-Jan Chao, Laung-Terng Wang:
A circular pipeline processing based deterministic parallel test pattern generator. ITC 2013: 1-8 - [c36]Jiun-Lang Huang, Kun-Han Tsai, Yu-Ping Liu, Ruifeng Guo
Improve speed path identification with suspect path expressions. VLSI-DAT 2013: 1-4 - [c35]Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang:
On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. VLSI Design 2013: 279-284 - 2012
- [j13]Xuan-Lun Huang, Jiun-Lang Huang, Hung-I Chen, Chang-Yu Chen, Tseng Kuo-Tsai, Ming-Feng Huang, Yung-Fa Chou, Ding-Ming Kwai:
An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration. J. Electron. Test. 28(5): 705-722 (2012) - [j12]Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang:
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. ACM Trans. Design Autom. Electr. Syst. 17(4): 48:1-48:16 (2012) - [c34]Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen:
A Transition Isolation Scan Cell Design for Low Shift and Capture Power. Asian Test Symposium 2012: 107-112 - [c33]Y.-H. Chou, Jiun-Lang Huang, Xuan-Lun Huang:
A Built-In Characterization Technique for 1-Bit/Stage Pipelined ADC. Asian Test Symposium 2012: 284-289 - [c32]Jiun-Lang Huang, X.-L. Huang, Yung-Fa Chou, Ding-Ming Kwai:
A SAR ADC missing-decision level detection and removal technique. VTS 2012: 31-36 - 2011
- [j11]Jiun-Lang Huang, Kwang-Ting (Tim) Cheng
A Promising Alternative to Conventional Silicon. IEEE Des. Test Comput. 28(6): 6 (2011) - [j10]Tsung-Ching Huang, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng
Robust Circuit Design for Flexible Electronics. IEEE Des. Test Comput. 28(6): 8-15 (2011) - [j9]Xuan-Lun Huang, Ping-Ying Kang, Yuan-Chi Yu, Jiun-Lang Huang:
Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs. J. Electron. Test. 27(4): 441-453 (2011) - [j8]Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu:
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 455-463 (2011) - [j7]Xuan-Lun Huang, Jiun-Lang Huang:
ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1765-1774 (2011) - [c31]Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu
A self-testing and calibration method for embedded successive approximation register ADC. ASP-DAC 2011: 713-718 - [c30]Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai:
A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. ETS 2011: 39-44 - [c29]Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen:
Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing. ITC 2011: 1-7 - 2010
- [c28]Meng-Fan Wu, Hsin-Cheih Pan, Teng-Han Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng:
Improved weight assignment for logic switching activity during at-speed test pattern generation. ASP-DAC 2010: 493-498 - [c27]Chun-Yong Liang, Meng-Fan Wu, Jiun-Lang Huang:
Power Supply Noise Reduction in Broadcast-Based Compression Environment for At-speed Scan Testing. Asian Test Symposium 2010: 361-366 - [c26]Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng
An error tolerance scheme for 3D CMOS imagers. DAC 2010: 917-922 - [c25]Jiun-Lang Huang, Kuo-Yu Chou, Ming-Huan Lu, Xuan-Lun Huang:
A robust ADC code hit counting technique. DATE 2010: 1749-1754 - [c24]Meng-Fan Wu, Kun-Han Tsai, Wu-Tung Cheng, Hsin-Cheih Pan, Jiun-Lang Huang, Augusli Kifli:
A scalable quantitative measure of IR-drop effects for scan pattern generation. ICCAD 2010: 162-167 - [c23]Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li:
CSER: BISER-based concurrent soft-error resilience. VTS 2010: 153-158 - [c22]Xuan-Lun Huang, Jiun-Lang Huang:
An ADC/DAC loopback testing methodology by DAC output offsetting and scaling. VTS 2010: 289-294
2000 – 2009
- 2009
- [j6]Meng-Fan Wu, Kai-Shun Hu, Jiun-Lang Huang:
LPTest: a Flexible Low-Power Test Pattern Generator. J. Electron. Test. 25(6): 323-335 (2009) - [j5]Chen-Wei Lin, Jiun-Lang Huang:
A Charge-Sensing-Capable Source Driver for TFT Array Testing in System-on-Panel Displays. J. Comput. 4(4): 338-346 (2009) - [j4]Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase:
Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1767-1776 (2009) - [c21]Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang:
Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input. ASP-DAC 2009: 775-780 - [c20]Chen-Yuan Yang, Xuan-Lun Huang, Jiun-Lang Huang:
An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing. Asian Test Symposium 2009: 367-372 - 2008
- [c19]Jui-Jer Huang, Chiuan-Che Li, Jiun-Lang Huang:
Testing LCD Source Driver IC with Built-on-Scribe-Line Test Circuitry. ATS 2008: 117-122 - [c18]Yi-Tsung Lin, Meng-Fan Wu, Jiun-Lang Huang:
PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment. ATS 2008: 391-396 - [c17]Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte:
On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. DFT 2008: 143-151 - [c16]Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase:
Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing. ITC 2008: 1-10 - [c15]Chen-Wei Lin, Jiun-Lang Huang:
A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays. VTS 2008: 169-174 - 2007
- [c14]Meng-Fan Wu, Kai-Shun Hu, Jiun-Lang Huang:
An Efficient Peak Power Reduction Technique for Scan Testing. ATS 2007: 111-114 - 2006
- [j3]Jiun-Lang Huang, Jui-Jer Huang, Yuan-Shuang Liu:
A Low-Cost Jitter Measurement Technique for BIST Applications. J. Electron. Test. 22(3): 219-228 (2006) - [j2]Jiun-Lang Huang:
On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines. J. Electron. Test. 22(4-6): 387-398 (2006) - [c13]Xuan-Lun Huang, Jiun-Lang Huang:
A routability constrained scan chain ordering technique for test power reduction. ASP-DAC 2006: 648-652 - [c12]Jiun-Lang Huang:
A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter. ATS 2006: 318-326 - 2005
- [c11]Jiun-Lang Huang:
Random Jitter Testing Using Low Tap-Count Delay Lines. Asian Test Symposium 2005: 100-105 - 2004
- [c10]Jui-Jer Huang, Jiun-Lang Huang:
An Infrastructure IP for On-Chip Clock Jitter Measurement. ICCD 2004: 186-191 - 2003
- [j1]Hao-Chiao Hong
Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems. IEEE Trans. Circuits Syst. II Express Briefs 50(9): 553-566 (2003) - [c9]Jui-Jer Huang, Jiun-Lang Huang:
A Low-Cost Jitter Measurement Technique for BIST Applications. Asian Test Symposium 2003: 336-339 - 2002
- [c8]Hao-Chiao Hong
On-chip Analog Response Extraction with 1-Bit ? - Modulators. Asian Test Symposium 2002: 49- - 2001
- [c7]Jiun-Lang Huang, Kwang-Ting Cheng:
An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links. VTS 2001: 380-387 - 2000
- [c6]Jiun-Lang Huang, Kwang-Ting Cheng
A sigma-delta modulation based BIST scheme for mixed-signal circuits. ASP-DAC 2000: 605-612 - [c5]Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng
A BIST Scheme for On-Chip ADC and DAC Testing. DATE 2000: 216-220 - [c4]Jiun-Lang Huang, Kwang-Ting Cheng:
Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis. ITC 2000: 1021-1030 - [c3]Jan Arild Tofte, Chee-Kian Ong, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng:
Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test. VTS 2000: 237-246
1990 – 1999
- 1999
- [c2]Jiun-Lang Huang, Chen-Yang Pan, Kwang-Ting Cheng:
Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits. VTS 1999: 220-225 - 1997
- [c1]Jiun-Lang Huang, Kwang-Ting Cheng
Analog Fault Diagnosis for Unpowered Circuit Boards. ITC 1997: 640-648
Coauthor Index
Kwang-Ting Cheng
aka: Kwang-Ting (Tim) Cheng
aka: Kwang-Ting (Tim) Cheng
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last updated on 2024-09-21 02:37 CEST by the dblp team
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