default search action
ITC 2000: Atlantic City, NJ, USA
- Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000. IEEE Computer Society 2000, ISBN 0-7803-6546-1
Session 2: System Test - Lecture Series
- L. Derere:
Case-based reasoning: diagnosis of faults in complex systems through reuse of experience. 27-34 - Jacob Savir:
On-line and off-line test of airborne digital systems: a reliability study. 35-44 - Stephen Harrison, Peter Collins, Greg Noeninckx:
The implementation of IEEE Std 1149.1 boundary scan test strategy within a cellular infrastructure production environment. 45-54
Session 3: Ate Software Generation
- Martin Bell, Givargis Danialy, Michael C. Howells, Stephen Pateras:
Bridging the gap between embedded test and ATE. 55-63 - Bruce R. Parnas:
Doing it in STIL: intelligent conversion from STIL to an ATE format. 64-71 - Andy Kittross:
Easy mixed signal test creation with test elements and procedures. 72-79
Session 4: Defect Behavior and Analysis Techniques
- Travis M. Eiles, Keneth R. Wilsher, William K. Lo, G. Xiao:
Optical interferometric probing of advanced microprocessors. 80-84 - Chien-Mo James Li, Edward J. McCluskey:
Testing for tunneling opens. 85-94 - Will R. Moore, Guido Gronthoud, Keith Baker, Maurice Lousberg:
Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything? 95-104
Session 5: Industrial Applications
- Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen
:
Application of deterministic logic BIST on industrial circuits. 105-114 - Debaleena Das, Nur A. Touba:
Reducing test data volume using external/LBIST hybrid test patterns. 115-122 - Michael Cogswell, Don Pearl, James Sage, Alan Troidl:
Test structure verification of logical BIST: problems and solutions. 123-130
Session 6: Microprocessor Test
- Rajesh Raina, Robert Bailey, Dawit Belete, Vikram Khosa, Robert F. Molyneaux, Javier Prado, Ashutosh Razdan:
DFT advances in Motorola's Next-Generation 74xx PowerPCTM microprocessor. 131-140 - Farideh Golshan:
Test and on-line debug capabilities of IEEE Std 1149.1 in UltraSPARC-III microprocessor. 141-150 - Teresa L. McLaurin, Frank Frederick:
The testability features of the MCF5407 containing the 4th generation ColdFire(R) microprocessor core. 151-159
Session 7: Systems Test
- Zan Yang, Byeong Min, Gwan Choi:
Si-emulation: system verification using simulation and emulation. 160-169 - Alfredo Benso, Silvia Chiusano, Paolo Prinetto:
A software development kit for dependable applications in embedded systems. 170-178 - Subhasish Mitra, Edward J. McCluskey:
Combinational logic synthesis for diversity in duplex systems. 179-188
Session 8: Practical I DDQ Testing For Deep-Submicron Designs
- W. Robert Daasch, James McNames, Daniel Bockelman, Kevin Cota:
Variance reduction using wafer patterns in I_ddQ data. 189-198 - Yukio Okuda:
DECOUPLE: defect current detection in deep submicron I_DDQ. 199-206 - Claude Thibeault:
Improving Delta-I_DDQ-based test methods. 207-216 - Pramodchandran N. Variyam:
Increasing the IDDQ test resolution using current prediction. 217-224
Session 9: Fault Diagnosis Algorithms And Techniques
- Xiaoming Yu, Jue Wu, Elizabeth M. Rudnick:
Diagnostic test generation for sequential circuits. 225-234 - Kazuki Shigeta, Toshio Ishiyama:
An improved fault diagnosis algorithm based on path tracing with dynamic circuit extraction. 235-244 - Pankaj Pant, Abhijit Chatterjee:
Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application. 245-252 - Srikanth Venkataraman, Scott Brady Drummonds:
POIROT: a logic fault diagnosis tool and its applications. 253-262
Session 10: Bist Techniques and Applications
- Subrata Roy, Gokhan Guner, Kwang-Ting Cheng:
Efficient test mode selection and insertion for RTL-BIST. 263-272 - Ismet Bayraktaroglu, Alex Orailoglu:
Deterministic partitioning techniques for fault diagnosis in scan-based BIST. 273-282 - Yasuo Sato, Toyohito Ikeya, Michinobu Nakao, Takaharu Nagumo:
A BIST approach for very deep sub-micron (VDSM) defects. 283-291 - M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor:
Test point insertion for compact test sets. 292-301
Session 11: Design Validation: From Function to Timing
- Qiushuang Zhang, Ian G. Harris:
A domain coverage metric for the validation of behavioral VHDL descriptions. 302-308 - Chung-Yang Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting Cheng:
Static property checking using ATPG vs. BDD techniques. 309-316 - Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta:
On validating data hold times for flip-flops in sequential circuits. 317-325 - Nabil M. Abdulrazzaq, Sandeep K. Gupta:
Test generation for path-delay faults in one-dimensional iterative logic arrays. 326-335
Session 12: Defect- Based Test Mehodologies And The Real World - Lecture Series
- Edward J. McCluskey, Chao-Wen Tseng:
Stuck-fault tests vs. actual defects. 336-343 - Ronald A. Richmond:
Successful implementation of structured testing. 344-348
Session 13: Test Techniques For ADCS
- Pramodchandran N. Variyam, Vinay Agrawal:
Measuring code edges of ADCs using interpolation and its application to offset and gain error testing. 349-357 - Sasikumar Cherubal, Abhijit Chatterjee:
Optimal INL/DNL testing of A/D converters using a linear model. 358-366 - Turker Kuyel, Frank (Ching-Yuh) Tsay:
Optimal analog trim techniques for improving the linearity of pipeline ADCs. 367-375
Session 14: Delay Fault Testing
- Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy:
Selection of potentially testable path delay faults for test generation. 376-384 - Manish Sharma, Janak H. Patel:
Enhanced delay defect coverage with path-segments. 385-392 - Haluk Konuk:
On invalidation mechanisms for non-robust delay tests. 393-399
Session 15: Optimizing Test Effectiveness
- Peter C. Maxwell, Ismed Hartanto, Lee Bentz:
Comparing functional and structural tests. 400-407 - Jayashree Saxena, Kenneth M. Butler:
An empirical study on the effects of test type ordering on overall test efficiency. 408-416 - Jais Abraham, Narayan Prasad, Srinivasa Chakravarthy B. S., Ameet Bagwe, Rubin A. Parekhji:
A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx. 417-425
Session 16: Momory Testing
- Ad J. van de Goor, A. Paalvast:
Industrial evaluation of DRAM SIMM tests. 426-435 - Harold Pilo, Stu Hall, Patrick Hansen, Steve Lamphier, Chris Murphy:
Design-for-test methods for stand-alone SRAMs at 1 Gb/s/pin and beyond. 436-443 - John Privitera, Steven Woo, Craig Soldat:
Pattern generation tools for the development of memory core test patterns for Rambus devices. 444-453
Session 17: Defect - Based Test Methodologies And The Real World - Lecture Series
- Phil Nigh, Anne E. Gattiker:
Test method evaluation experiments and data. 454-463 - Mike Rodgers:
Defect screening challenges in the Gigahertz/Nanometer age: keeping up with the tails of defect behaviors. 464-467
Session 18: From Tester to Applications - Beginning to End
- Jerry Katz, Rochit Rajsuman:
A new paradigm in test for the next millennium. 468-476 - Jerry J. Broz, James C. Andersen, Reynaldo M. Rincon:
Reducing device yield fallout at wafer level test with electrohydrodynamic (EHD) cleaning. 477-484 - Cristo da Costa:
Hardware for production test of RFID interface embedded into chips for smart cards and labels used in contactless applications. 485-491
Session 19: Test For Crosstalk and Bridging Faults
- Yi Zhao, Sujit Dey:
Analysis of interconnect crosstalk defect coverage of test sets. 492-501 - Rahul Kundu, Ronald D. Blanton:
Identification of crosstalk switch failures in domino CMOS circuits. 502-509 - Toshiyuki Maeda, Kozo Kinoshita:
Precise test generation for resistive bridging faults of CMOS combinational circuits. 510-519
Session 20: Advances In Test Generation
- Dong Xiang, Yi Xu, Hideo Fujiwara:
Non-scan design for testability for synchronous sequential circuits based on conflict analysis. 520-529 - Robert Butler, Brion L. Keller, Sarala Paliwal, Richard Schoonover, Joseph Swenton:
Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count. 530-537 - Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr:
Exploiting don't cares to enhance functional tests. 538-546
Session 21: Embedde Memories Test And Repair
- Kamran Zarrineh, R. Dean Adams, Thomas J. Eckenrode, Steven P. Gregor:
Self test architecture for testing complex memory structures. 547-556 - Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni:
A programmable BIST architecture for clusters of multiple-port SRAMs. 557-566 - Tomoya Kawagoe, Jun Ohtani, Mitsutaka Niiro, Tukasa Ooishi, Mitsuhiro Hamada, Hideto Hidaka:
A built-in self-repair analyzer (CRESTA) for embedded DRAMs. 567-574
Session 22: Board Test
- Frans G. M. de Jong, Ben Kup, Rodger Schuttert:
Power pin testing: making the test coverage complete. 575-584 - Robert W. Barr, Chen-Huan Chiang, Edward L. Wallace:
End-to-end testing for boards and systems using boundary scan. 585-592 - David McClintock, Lance Cunningham, Takis Petropoulos:
Motherboard testing using the PCI bus. 593-599
Session 23: Tester Hardware Issues In Leaping To 1GHZ
- Yongming Cai, T. P. Warwick, Sunil G. Rane, E. Masserrat:
Digital serial communication device testing and its implications on automatic test equipment architecture. 600-609 - Dieu Van Dinh, Virginia Rabitoy:
An approach to testing 200 ps echo clock to output timing on the double data rate synchronous memory. 610-618 - Luca Sartori, Burnell G. West:
The path to one-picosecond accuracy. 619-627
Session 24: Soc Test Solutions
- Steven F. Oakland:
Considerations for implementing IEEE 1149.1 on system-on-a-chip integrated circuits. 628-637 - Helmut Lang, Jens Pfeiffer, Jeff Maguire:
Using on-chip test pattern compression for full scan SoC designs. 638-643 - Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich:
Non-intrusive BIST for systems-on-a-chip. 644-651
Session 25: Low-Power Bist
- Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch:
Low power BIST design by hypergraph partitioning: methodology and architectures. 652-661 - Nicola Nicolici, Bashir M. Al-Hashimi:
Power conscious test synthesis and scheduling for BIST RTL data paths. 662-671 - David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre:
BISTing data paths at behavioral level. 672-680
Session 26: Methodology And Tools For Microprocessor Test
- Peter Wohl, John A. Waicukauski:
Optimizing the flattened test-generation model for very large designs. 681-690 - Don E. Ross, Tim Wood, Grady Giles:
Conversion of small functional test sets of nonscan blocks to scan patterns. 691-700 - Anjali Kinra, Hari Balachandran, Regy Thomas, John Carulli:
Logic mapping on a microprocessor. 701-710
Session 27: Board Test - lecture Series
- Julia A. Keahey:
Programming of flash with ICT rights and responsibilities. 711-717 - Stephen F. Scheiber:
It isn't just testing anymore (REDUX). 718-723 - Kenneth P. Parker:
System issues in boundary-scan board test. 724-728
Session 28: Extraction Test And Diagnosis Of Physical Defects
- Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler:
Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. 729-738 - Nilmoni Deb, Ronald D. Blanton:
Analysis of failure sources in surface-micromachined MEMS. 739-749 - Sujit T. Zachariah, Sreejit Chakravarty:
A scalable and efficient methodology to extract two node bridges from large industrial circuits. 750-759 - Charles E. Stroud, John Marty Emmert, John R. Bailey, Khushru S. Chhor, Dragan Nikolic:
Bridging fault extraction from physical design data for manufacturing test development. 760-769
Session 29: Use Models Of IEEE P1500
- Yervant Zorian, Erik Jan Marinissen, Rohit Kapur:
On using IEEE P1500 SECT for test plug-n-play. 770-777
Session 30: Quality Bist FOr Logic And FPGA
- Sybille Hellebrand, Hans-Joachim Wunderlich, Huaguo Liang:
A mixed mode BIST scheme based on reseeding of folding counters. 778-784 - Miron Abramovici, Charles E. Stroud:
DIST-based detection and diagnosis of multiple faults in FPGAs. 785-794 - Xiaoling Sun, Jian Xu, Ben Chan, Pieter M. Trouborst:
Novel technique for built-in self-test of FPGA interconnects. 795-803 - Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register. 804-811
Session 31: Detecting All Types Of Faults TS Quickly
- Rao Desineni, Kumar N. Dwarakanath, Ronald D. Blanton:
Universal test generation using fault tuples. 812-819 - Thomas Bartenstein:
Fault distinguishing pattern generation. 820-828 - Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
: Reducing test application time in high-level test generation. 829-838 - Qiang Peng, Miron Abramovici, Jacob Savir:
MUST: multiple-stem analysis for identifying sequentially untestable faults. 839-846
Session 32: FPGA- Lecture Series
- Neil G. Jacobson:
Streamlining programmable device and system test using IEEE Std 1532. 847-853 - Michel Renovell, Yervant Zorian:
Different experiments in test generation for XILINX FPGAs. 854-862
Session 33: Test Techniques for Low-Power Optimization
- Lee Whetsel:
Adapting scan architectures for low power operation. 863-872 - Bahram Pouya, Alfred L. Crouch:
Optimization trade-offs for vector volume and test power. 873-881 - Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu:
A comparison of classical scheduling approaches in power-constrained block-test scheduling. 882-891
Session 34: Test Access Design For Soc'S
- Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Fabio Ricciato, Maurizio Spadari, Yervant Zorian:
HD2BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs. 892-901 - Mehrdad Nourani, Christos A. Papachristou:
An ILP formulation to optimize test access mechanism in system-on-chip testing. 902-910 - Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel:
Wrapper design for embedded core test. 911-920
Session 35: How Do We Know If Fault Models Areacurate?
- Peter C. Maxwell, Jeff Rearick:
Deception by design: fooling ourselves with gate-level models. 921-929 - Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer:
Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D. 930-939 - Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul:
Register-transfer level fault modeling and test evaluation techniques for VLSI circuits. 940-949
Session 36: High-Frequence Test Techniques
- Peter M. Higgins, Jim Lampos:
Microwave test mismatch and power de-embedding. 950-954 - Takahiro J. Yamaguchi, Mani Soma, David Halter, Jim Nissen, Rajesh Raina, Masahiro Ishida, Toshifumi Watanabe:
Jitter measurements of a PowerPCTM microprocessor using an analytic signal method. 955-964 - Doug Matthes, John Ford:
Technique for testing a very high speed mixed signal read channel design. 965-970
Session 37: Concurrent Error Detection
- Ramesh Karri
Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique. 971-978 - Santiago Fernández-Gomez, Juan J. Rodríguez-Andina
Concurrent error detection in block ciphers. 979-984 - Subhasish Mitra, Edward J. McCluskey:
Which concurrent error detection scheme to choose ? 985-994
Session 38: The Final Furdle-Signals And Power To the Dut
- Ulrich Schoettmer, Chris Wagner, Tom Bleakley:
Device interfacing: the weakest link in the chain to break into the giga bit domain? 995-1004 - Ulf Pillkahn:
Structural test in a board self test environment. 1005-1012 - Gerald H. Johnson:
Challenges of high supply currents during VLSI test. 1013-1020
Session 39: Mixed-Signal BIST
- Jiun-Lang Huang, Kwang-Ting Cheng:
Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis. 1021-1030 - Mohamed M. Hafed, Nazmy Abaskharoun, Gordon W. Roberts:
A stand-alone integrated test core for time and frequency domain measurements. 1031-1040 - Anna Maria Brosa, Joan Figueras:
Digital signature proposal for mixed-signal circuits. 1041-1050
Session 40: New Methods For Delay Testing
- Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, Krishnamurthy Soumyanath, Vivek De:
Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. 1051-1059 - Seonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota:
An analysis of the delay defect detection capability of the ECR test method. 1060-1069 - James F. Plusquellic, Amy Germida, Jonathan Hudson, Ernesto Staroswiecki, Chintan Patel:
Predicting device performance from pass/fail transient signal analysis data. 1070-1079
Session 41: Processor Core Test Techniques
- Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng:
Test program synthesis for path delay faults in microprocessor cores. 1080-1089 - David B. Lavo:
A good excuse for reuse: "open" TAP controller design. 1090-1099 - Teresa L. McLaurin, John C. Potter:
On-the-shelf core pattern methodology for ColdFire(R) microprocessor cores. 1100-1107 - Peter C. Maxwell, Pete O'Neill, Robert C. Aitken, Ronald Dudley, Neal Jaarsma, Minh Quach, Don Wiseman:
Current ratios: a self-scaling technique for production IDDQ testing. 1148-1156
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-20 21:07 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: