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"FPGA-Based Subset Sum Delay Lines."

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Chung-Yun Wang et al. (2014)

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DOI: 10.1109/ATS.2014.60

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Chung-Yun Wang, Yu-Yi Chen, Jiun-Lang Huang, Xuan-Lun Huang:
FPGA-Based Subset Sum Delay Lines. ATS 2014: 287-291

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last updated on 2023-03-24 00:02 CET by the dblp team

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