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Yung-Fa Chou
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2020 – today
- 2020
- [j10]Chia-Hua Wu, Shi-Yu Huang
, Yung-Fa Chou, Ding-Ming Kwai
Time-to-Digital Converter Compiler for On-Chip Instrumentation. IEEE Des. Test 37(4): 101-107 (2020) - [c42]Tsung-Fu Hsieh, Jin-Fu Li, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method. ITC-Asia 2020: 41-46
2010 – 2019
- 2018
- [c41]Kuan-Te Wu, Jin-Fu Li, Chih-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou:
A channel-sharable built-in self-test scheme for multi-channel DRAMs. ASP-DAC 2018: 245-250 - [c40]Jia-Yun Hu, Kuan-Wei Hou, Chih-Yen Lo, Yung-Fa Chou, Cheng-Wen Wu
RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction. ITC-Asia 2018: 19-24 - 2017
- [c39]Wei-Hsun Liao, Chang-Tzu Lin, Sheng-Hsin Fang, Chien-Chia Huang, Hung-Ming Chen, Ding-Ming Kwai, Yung-Fa Chou:
Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization. ASP-DAC 2017: 549-553 - [c38]Chia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou:
DLL-Assisted Clock Synchronization Method for Multi-Die ICs. ICCD 2017: 473-476 - [c37]Tah-Kang Joseph Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chun-Kai Wang, Chun-Wei Lo, Li-Chin Tien, Der-Min Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, Ding-Ming Kwai, Zhe Wang, Wei Wu, Shigeki Tomishima
23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. ISSCC 2017: 404-405 - [c36]Chia-Hua Wu, Shi-Yu Huang, Mason Chern, Yung-Fa Chou, Ding-Ming Kwai:
Resilient Cell-Based Architecture for Time-to-Digital Converter. ISVLSI 2017: 7-12 - [c35]Sheng-Hsin Fang, Chang-Tzu Lin, Wei-Hsun Liao, Chien-Chia Huang, Li-Chin Chen, Hung-Ming Chen, I-Hsuan Lee, Ding-Ming Kwai, Yung-Fa Chou:
On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC. ISVLSI 2017: 459-464 - [c34]Tsung-Fu Hsieh, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs. ITC-Asia 2017: 107-111 - 2016
- [c33]Tzu-Ying Lin, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
A Test Method for Finding Boundary Currents of 1T1R Memristor Memories. ATS 2016: 281-286 - [c32]Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. ITC 2016: 1-7 - 2015
- [j9]Che-Wei Chou, Jin-Fu Li, Yun-Chao Yu, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Hierarchical Test Integration Methodology for 3-D ICs. IEEE Des. Test 32(4): 59-70 (2015) - [c31]Hua-Cheng Fu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou:
Temperature-aware online testing of power-delivery TSVs. 3DIC 2015: TS10.3.1-TS10.3.6 - [c30]Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou:
A hybrid built-in self-test scheme for DRAMs. VLSI-DAT 2015: 1-4 - [c29]Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. VLSIC 2015: 186- - 2014
- [j8]Yen-Lin Peng, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 207-219 (2014) - [c28]Yun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. ATS 2014: 1-6 - [c27]Kuan-Te Wu, Jin-Fu Li, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo:
Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs. ATS 2014: 143-148 - [c26]Tsu-Wei Tseng, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai:
A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage. VLSI-DAT 2014: 1-4 - 2013
- [j7]Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai:
Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 737-747 (2013) - [j6]Ji-Wei Ker, Shi-Yu Huang, Chao-Wen Tzeng, Ding-Ming Kwai, Yung-Fa Chou:
Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(4): 908-917 (2013) - [j5]Yung-Fa Chou, Ding-Ming Kwai, Ming-Der Shieh, Cheng-Wen Wu
Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(9): 2343-2351 (2013) - [j4]Jhih-Wei You, Shi-Yu Huang, Yu-Hsiang Lin, Meng-Hsiu Tsai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 443-453 (2013) - [c25]Chi-Wen Pan, Yu-Min Lee, Pei-Yu Huang, Chi-Ping Yang, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai:
I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs. ASP-DAC 2013: 151-156 - [c24]Chih-Sheng Hou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
An FPGA-based test platform for analyzing data retention time distribution of DRAMs. VLSI-DAT 2013: 1-4 - [c23]Chen-Hsiang Hsu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou:
Worst-case IR-drop monitoring with 1GHz sampling rate. VLSI-DAT 2013: 1-4 - [c22]Chang-Tzu Lin, Tsu-Wei Tseng, Yung-Fa Chou, Chia-Hsin Lee, Ding-Ming Kwai:
Enabling inter-die co-optimization in 3-D IC with TSVs. VLSI-DAT 2013: 1-4 - [c21]Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. VTS 2013: 1-6 - 2012
- [j3]Xuan-Lun Huang, Jiun-Lang Huang, Hung-I Chen, Chang-Yu Chen, Tseng Kuo-Tsai, Ming-Feng Huang, Yung-Fa Chou, Ding-Ming Kwai:
An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration. J. Electron. Test. 28(5): 705-722 (2012) - [c20]Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai:
Small delay testing for TSVs in 3-D ICs. DAC 2012: 1031-1036 - [c19]Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A built-in self-test scheme for 3D RAMs. ITC 2012: 1-9 - [c18]Chun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao, Cheng-Wen Wu
3D-IC BISR for stacked memories using cross-die spares. VLSI-DAT 2012: 1-4 - [c17]Chang-Tzu Lin, Chia-Hsin Lee, Tsu-Wei Tseng, Ding-Ming Kwai, Yung-Fa Chou:
3-D centric technology and realization with TSV. VLSI-DAT 2012: 1-4 - [c16]Jiun-Lang Huang, X.-L. Huang, Yung-Fa Chou, Ding-Ming Kwai:
A SAR ADC missing-decision level detection and removal technique. VTS 2012: 31-36 - 2011
- [j2]Yung-Fa Chou, Ding-Ming Kwai, Cheng-Wen Wu
Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1346-1356 (2011) - [c15]Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu
A self-testing and calibration method for embedded successive approximation register ADC. ASP-DAC 2011: 713-718 - [c14]Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai:
A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. ETS 2011: 39-44 - [c13]Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. VTS 2011: 20-25 - 2010
- [c12]Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen Ching Wu:
CAD reference flow for 3D via-last integrated circuits. ASP-DAC 2010: 187-192 - [c11]Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A Test Integration Methodology for 3D Integrated Circuits. Asian Test Symposium 2010: 377-382 - [c10]Jhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Performance Characterization of TSV in 3D IC via Sensitivity Analysis. Asian Test Symposium 2010: 389-394
2000 – 2009
- 2007
- [j1]Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou, Cheng-Wen Wu
Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1101-1113 (2007) - 2006
- [c9]Ding-Ming Kwai, Yung-Fa Chou, Meng-Fan Chang, Su-Meng Yang, Ding-Sheng Chen, Min-Chung Hsu, Yu-Zhen Liao, Shiao-Yi Lin, Yu-Ling Sung, Chia-Hsin Lee, Hsin-Kun Hsu:
FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment. MTDT 2006: 28-33 - [c8]Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, Chi-Hsien Chuang, Min-Chung Hsu, Yi-Chun Chen, Yu-Ling Sung, Hsien-Yu Pan, Chia-Hsin Lee, Meng-Fan Chang, Yung-Fa Chou:
SRAM Cell Current in Low Leakage Design. MTDT 2006: 65-70 - 2004
- [c7]Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu:
SRAM delay fault modeling and test algorithm development. ASP-DAC 2004: 104-109 - 2003
- [c6]Rei-Fu Huang, Yung-Fa Chou, Cheng-Wen Wu
Defect Oriented Fault Analysis for SRAM. Asian Test Symposium 2003: 256-261 - [c5]Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu:
FAME: A Fault-Pattern Based Memory Failure Analysis Framework. ICCAD 2003: 595-598 - [c4]Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang:
Fault Pattern Oriented Defect Diagnosis for Memories. ITC 2003: 29-38 - 2002
- [c3]Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
Flash Memory Built-In Self-Test Using March-Like Algorithm. DELTA 2002: 137-141 - 2000
- [c2]Ding-Ming Kwai, Hung-Wen Chang, Hung-Jen Liao, Ching-Hua Chiao, Yung-Fa Chou:
etection of SRAM cell stability by lowering array supply voltage. Asian Test Symposium 2000: 268-273
1990 – 1999
- 1994
- [c1]Cheng-Wen Wu, Yung-Fa Chou:
General Modular Multiplication by Block Multiplication and Table Lookup. ISCAS 1994: 295-298
Coauthor Index
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