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Sadami Takeoka
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2000 – 2009
- 2005
- [j2]Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka:
On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis. IEICE Trans. Inf. Syst. 88-D(7): 1671-1677 (2005) - 2003
- [j1]Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka, Shinichi Yoshimura:
Evaluation of Delay Testing Based on Path Selection. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3208-3210 (2003) - [c4]Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka, Shinichi Yosimura:
On effective criterion of path selection for delay testing. ASP-DAC 2003: 757-762 - [c3]Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka:
On Estimation of Fault Efficiency for Path Delay Faults. Asian Test Symposium 2003: 64-67 - 2000
- [c2]Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta:
On validating data hold times for flip-flops in sequential circuits. ITC 2000: 317-325
1990 – 1999
- 1995
- [c1]Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka:
Design for testability using register-transfer level partial scan selection. ASP-DAC 1995
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