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Dimitris Nikolos
Dimitris G. Nikolos
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- affiliation: University of Patras, Greece
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2020 – today
- 2024
- [c83]Michail Mavropoulos, Georgios Keramidas, Dimitris Nikolos:
Improving the Performance Predictability of Faulty Data Caches. EDCC 2024: 123-130 - 2022
- [j45]Michail Mavropoulos
, Georgios Keramidas, Dimitris Nikolos:
Enabling efficient sub-block disabled caches using coarse grain spatial predictions. Microprocess. Microsystems 90: 104479 (2022) - 2021
- [c82]Michail Mavropoulos, Georgios Keramidas, Dimitris Nikolos:
Run Time Management of Faulty Data Caches. ETS 2021: 1-6
2010 – 2019
- 2018
- [c81]Filippos Filippou, Georgios Keramidas, Michail Mavropoulos, Dimitris Nikolos:
A novel fault tolerant cache architecture based on orthogonal latin squares theory. DATE 2018: 1429-1434 - 2016
- [c80]Filippos Filippou, Georgios Keramidas, Michail Mavropoulos, Dimitris Nikolos:
Recovery of performance degradation in defective branch target buffers. IOLTS 2016: 96-102 - [c79]Panagiotis Sismanoglou, Dimitris Nikolos:
Conditional soft-edge flip-flop for SET mitigation. IOLTS 2016: 227-232 - [c78]Panagiotis Sismanoglou, Dimitris Nikolos:
Low capture power dictionary-based test data compression. ISQED 2016: 289-294 - 2015
- [c77]Michail Mavropoulos, Georgios Keramidas, Dimitris Nikolos:
A defect-aware reconfigurable cache architecture for low-vccmin DVFS-enabled systems. DATE 2015: 417-422 - [c76]Michail Mavropoulos, Georgios Keramidas, Grigorios Adamopoulos, Dimitris Nikolos:
Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled Systems. ACM Great Lakes Symposium on VLSI 2015: 161-166 - [c75]Panagiotis Sismanoglou, Vlasis Pitsios, Dimitris Nikolos:
Preemptive built-in self-test for in-field structural testing. ISQED 2015: 154-161 - 2014
- [c74]Georgios Keramidas, Michail Mavropoulos, Anna Karvouniari, Dimitris Nikolos:
Spatial pattern prediction based management of faulty data caches. DATE 2014: 1-6 - [c73]Panagiotis Sismanoglou, Dimitris Nikolos:
Test data compression based on reuse and bit-flipping of parts of dictionary entries. DDECS 2014: 110-115 - 2013
- [j44]Panagiotis Sismanoglou, Dimitris Nikolos:
Input Test Data Compression Based on the Reuse of Parts of Dictionary Entries: Static and Dynamic Approaches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1762-1775 (2013) - [c72]Panagiotis Sismanoglou, Dimitris Nikolos:
Enhancing dictionary based test data compression using the ATE repeat instruction. ICECS 2013: 401-404 - 2011
- [c71]Panagiotis Sismanoglou, Dimitris Nikolos:
Test data compression based on the reuse of parts of the dictionary entries. ICECS 2011: 538-541
2000 – 2009
- 2009
- [j43]Dimitris Nikolos, Dimitrios Kagaris, Samara Sudireddy, Spyros Gidaros:
An Improved Search Method for Accumulator-Based Test Set Embedding. IEEE Trans. Computers 58(1): 132-138 (2009) - [j42]Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
Efficient partial scan cell gating for low-power scan-based testing. ACM Trans. Design Autom. Electr. Syst. 14(2): 28:1-28:15 (2009) - [c70]M. Koutsoupia, Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos:
LFSR-based test-data compression with self-stoppable seeds. DATE 2009: 1482-1487 - 2008
- [j41]Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1333-1338 (2008) - [j40]Giorgos Dimitrakopoulos
Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 837-850 (2008) - [j39]Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 926-931 (2008) - 2007
- [j38]Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
Optimal Selective Huffman Coding for Test-Data Compression. IEEE Trans. Computers 56(8): 1146-1152 (2007) - [j37]Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1070-1083 (2007) - [j36]Themistoklis Haniotakis, Y. Tsiatouhas
Testable Designs of Multiple Precharged Domino Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 461-465 (2007) - [j35]Giorgos Dimitrakopoulos
Sorter Based Permutation Units for Media-Enhanced Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 711-715 (2007) - 2006
- [j34]Dimitris Bakalis, Kostas Adaos, Dimitrios Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos:
A core generator for arithmetic cores and testing structures with a network interface. J. Syst. Archit. 52(1): 1-12 (2006) - [j33]Dimitrios Kagaris, P. Karpodinis, Dimitris Nikolos:
On Obtaining Maximum-Length Sequences for Accumulator-Based Serial TPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2578-2586 (2006) - [c69]Giorgos Dimitrakopoulos
An Energy-Delay Efficient Subword Permutation Unit. ASAP 2006: 245-252 - [c68]Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
Efficient test-data compression for IP cores using multilevel Huffman coding. DATE 2006: 1033-1038 - [c67]Dimitris Nikolos, Dimitrios Kagaris, Spyros Gidaros:
Diophantine-Equation Based Arithmetic Test Set Embedding. IOLTS 2006: 193-194 - [c66]Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos:
Fast bit permutation unit for media enhanced microprocessors. ISCAS 2006 - [c65]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos:
Efficient Multiphase Test Set Embedding for Scan-based Testing. ISQED 2006: 433-438 - 2005
- [j32]Giorgos Dimitrakopoulos
High-Speed Parallel-Prefix VLSI Ling Adders. IEEE Trans. Computers 54(2): 225-231 (2005) - [j31]Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos
Efficient Diminished-1 Modulo 2^n+1 Multipliers. IEEE Trans. Computers 54(4): 491-496 (2005) - [c64]Maciej Bellos, Dimitris Nikolos:
Deterministic Test Vector Compression / Decompression Using an Embedded Processor. EDCC 2005: 318-331 - [c63]Giorgos Dimitrakopoulos
New architectures for modulo 2N - 1 adders. ICECS 2005: 1-4 - [c62]Giorgos Dimitrakopoulos
New architectures for modulo 2N - 1 adders. ICECS 2005: 1-4 - [c61]George Gekas, Dimitris Nikolos, Emmanouil Kalligeros, Xrysovalantis Kavousianos:
Power aware test-data compression for scan-based testing. ICECS 2005: 1-4 - [c60]Emmanouil Kalligeros, D. Kaseridis, Xrysovalantis Kavousianos, Dimitris Nikolos:
Reseeding-Based Test Set Embedding with Reduced Test Sequences. ISQED 2005: 226-231 - [c59]Giorgos Dimitrakopoulos, Dimitris Nikolos:
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing. PATMOS 2005: 308-317 - 2004
- [j30]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
Modified Booth Modulo 2n-1 Multipliers. IEEE Trans. Computers 53(3): 370-374 (2004) - [j29]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
Fast Parallel-Prefix Modulo 2^n+1 Adders. IEEE Trans. Computers 53(9): 1211-1216 (2004) - [j28]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos:
Multiphase BIST: a new reseeding technique for high test-data compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(10): 1429-1446 (2004) - [c58]Costas Laoudias, Dimitris Nikolos:
A new test pattern generator for high defect coverage in a BIST environment. ACM Great Lakes Symposium on VLSI 2004: 417-420 - [c57]P. Karpodinis, Dimitri Kagaris, Dimitris Nikolos:
Accumulator based Test-per-Scan BIST. IOLTS 2004: 193-198 - [c56]Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos:
Low Power Testing by Test Vector Ordering with Vector Repetition. ISQED 2004: 205-210 - [c55]Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos:
Scan Cell Ordering for Low Power BIST. ISVLSI 2004: 281-284 - [c54]Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos:
An Efficient Test Vector Ordering Method for Low Power Testing. ISVLSI 2004: 285-288 - [c53]Giorgos Dimitrakopoulos, Pavlos Kolovos, P. Kalogerakis, Dimitris Nikolos:
Design of High-Speed Low-Power Parallel-Prefix VLSI Adders. PATMOS 2004: 248-257 - 2003
- [j27]Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou:
Deterministic BIST for RNS Adders. IEEE Trans. Computers 52(7): 896-906 (2003) - [j26]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
Modulo 2n±1 Adder Design Using Select-Prefix Blocks. IEEE Trans. Computers 52(11): 1399-1406 (2003) - [c52]Giorgos Dimitrakopoulos
A Family of Parallel-Pre.x Modulo 2n - 1 Adders. ASAP 2003: 326-336 - [c51]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos:
A highly regular multi-phase reseeding technique for scan-based BIST. ACM Great Lakes Symposium on VLSI 2003: 295-298 - [c50]Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos
Efficient modulo 2n+1 tree multipliers for diminished-1 operands. ICECS 2003: 200-203 - [c49]Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou:
An Efficient BIST scheme for High-Speed Adders. IOLTS 2003: 89-93 - [c48]Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou:
An Efficient BIST scheme for High-Speed Adders. IOLTS 2003: 89-93 - [c47]Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
A systematic methodology for designing area-time efficient parallel-prefix modulo 2n - 1 adders. ISCAS (5) 2003: 225-228 - [c46]Giorgos Dimitrakopoulos, Xrysovalantis Kavousianos, Dimitris Nikolos:
Virtual-scan: a novel approach for software-based self-testing of microprocessors. ISCAS (5) 2003: 237-240 - [c45]Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou:
Efficient BIST schemes for RNS datapaths. ISCAS (5) 2003: 573-576 - [c44]Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou:
Efficient BIST schemes for RNS datapaths. ISCAS (5) 2003: 573-576 - [c43]Maciej Bellos, Dimitri Kagaris, Dimitris Nikolos:
Low Power Test Set Embedding Based on Phase Shifters. ISVLSI 2003: 155-160 - [c42]Maciej Bellos, Xrysovalantis Kavousianos, Dimitris Nikolos, Dimitri Kagaris:
DV-TSE: Difference Vector Based Test Set Embedding. VLSI-SOC 2003: 343- - 2002
- [j25]Dimitris Nikolos, John P. Hayes, Michael Nicolaidis, Cecilia Metra:
Guest Editorial. J. Electron. Test. 18(3): 259-260 (2002) - [j24]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST. J. Electron. Test. 18(3): 315-332 (2002) - [j23]Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni:
A new technique for IDDQ testing in nanometer technologies. Integr. 31(2): 183-194 (2002) - [j22]Dimitris Bakalis, Emmanouil Kalligeros, Dimitris Nikolos, Haridimos T. Vergos, George Alexiou:
On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation. J. Syst. Archit. 48(4-5): 125-135 (2002) - [j21]Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos:
Diminished-One Modulo 2n+1 Adder Design. IEEE Trans. Computers 51(12): 1389-1399 (2002) - [j20]Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas:
A new built-in TPG method for circuits with random patternresistant faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7): 859-866 (2002) - [c41]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos:
A ROMless LFSR Reseeding Scheme for Scan-based BIST. Asian Test Symposium 2002: 206- - [c40]Maciej Bellos, Dimitrios Kagaris, Dimitris Nikolos:
Test Set Embedding Based on Phase Shifters. EDCC 2002: 90-101 - [c39]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
Ling adders in CMOS standard cell technologies. ICECS 2002: 485-488 - [c38]Y. Tsiatouhas
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. IOLTW 2002: 56-60 - [c37]Giorgos Dimitrakopoulos
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. IOLTW 2002: 152-157 - [c36]Y. Tsiatouhas
Extending the Viability of IDDQ Testing in the Deep Submicron Era. ISQED 2002: 100-105 - [c35]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. ISQED 2002: 261-266 - 2001
- [j19]Dimitris Bakalis, Xrysovalantis Kavousianos, Haridimos T. Vergos, Dimitris Nikolos, G. Ph. Alexiou:
Low Power Built-In Self-Test Schemes for Array and Booth Multipliers. VLSI Design 12(3): 431-448 (2001) - [c34]Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. IEEE Symposium on Computer Arithmetic 2001: 211-217 - [c33]Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
A novel reseeding technique for accumulator-based test pattern generation. ACM Great Lakes Symposium on VLSI 2001: 7-12 - [c32]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
On the design of modulo 2n±1 adders. ICECS 2001: 517-520 - [c31]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
A New Reseeding Technique for LFSR-Based Test Pattern Generation. IOLTW 2001: 80-86 - [c30]Y. Tsiatouhas
Concurrent Detection of Soft Errors Based on Current Monitoring. IOLTW 2001: 106-110 - [c29]Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos:
On Accumulator-Based Bit-Serial Test Response Compaction Schemes. ISQED 2001: 350-355 - [c28]Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou:
A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme. LATW 2001: 242-247 - [c27]Dimitris Bakalis, Kostas Adaos, George Alexiou, Dimitris Nikolos, Dimitrios Lymperopoulos:
EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores. IEEE International Workshop on Rapid System Prototyping 2001: 182-187 - 2000
- [j18]Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos:
High-Speed Parallel-Prefix Modulo 2n-1 Adders. IEEE Trans. Computers 49(7): 673-680 (2000) - [j17]Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos:
Novel Single and Double Output TSC CMOS Checkers for m-out-of-n Codes. VLSI Design 11(1): 35-45 (2000) - [c26]Y. Tsiatouhas
A Versatile Built-In Self-Test Scheme for Delay Fault Testing. DATE 2000: 756 - [c25]Y. Tsiatouhas
A Compact Built-In Current Sensor for IDDQ Testing. IOLTW 2000: 95-99 - [c24]Th. Haniotakis, Y. Tsiatouhas
On Testability of Multiple Precharged Domino Logic. ISQED 2000: 299-304 - [c23]Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos:
Low Power BIST for Wallace Tree-Based Fast Multipliers. ISQED 2000: 433-438 - [c22]Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register. ITC 2000: 804-811
1990 – 1999
- 1999
- [j16]Ioannis Voyiatzis, Antonis M. Paschalis
An Accumulator-Based BIST Approach for Two-Pattern Testing. J. Electron. Test. 15(3): 267-278 (1999) - [j15]Xrysovalantis Kavousianos, Dimitris Nikolos, G. Foukarakis, T. Gnardellis:
New efficient totally self-checking Berger code checkers. Integr. 28(1): 101-118 (1999) - [j14]Dimitris Nikolos, Haridimos T. Vergos:
On the Yield of VLSI Processors with On-Chip CPU Cache. IEEE Trans. Computers 48(10): 1138-1144 (1999) - [c21]G. Sidiropoulos, Haridimos T. Vergos, Dimitris Nikolos:
Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers. Asian Test Symposium 1999: 47-52 - [c20]Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. DATE 1999: 112-116 - [c19]Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou:
Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. DFT 1999: 121-129 - [c18]Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos:
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. EDCC 1999: 267-282 - [c17]Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis:
On Path Delay Fault Testing of Multiplexer - Based Shifters. Great Lakes Symposium on VLSI 1999: 20-23 - [c16]Haridimos T. Vergos, Maciej Bellos, Dimitris Nikolos:
Path delay fault testing of Benes multistage interconnection networks. ICECS 1999: 1097-1100 - [c15]C. Ninos, Haridimos T. Vergos, Dimitris Nikolos:
Design and Analysis of On-Chip CPU Pipelined Caches. VLSI 1999: 161-172 - [c14]A. Vasilliou, K. Gounaris
Development of a Reusable E1 Transceiver Suitable for Rapid Prototyping. IEEE International Workshop on Rapid System Prototyping 1999: 21- - [c13]Xrysovalantis Kavousianos, Dimitris Nikolos:
Modular TSC Checkers for Bose-Lin and Bose Codes. VTS 1999: 354-360 - 1998
- [j13]Dimitris Nikolos:
Self-Testing Embedded Two-Rail Checkers. J. Electron. Test. 12(1-2): 69-79 (1998) - [j12]Dimitris Nikolos:
Optimal Self-Testing Embedded Parity Checkers. IEEE Trans. Computers 47(3): 313-321 (1998) - [c12]Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas
C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. DFT 1998: 155-163 - [c11]Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantinos Halatsis:
R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique. ITC 1998: 918-925 - [c10]Xrysovalantis Kavousianos, Dimitris Nikolos:
Novel Single and Double Output TSC Berger Code Checkers. VTS 1998: 348-353 - 1997
- [c9]Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos:
Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes. DFT 1997: 128-136 - [c8]Xrysovalantis Kavousianos, Dimitris Nikolos:
Self-exercising self testing k-order comparators. VTS 1997: 216-221 - 1996
- [j11]Ioannis Voyiatzis, Antonis M. Paschalis
An efficient built-in self test method for robust path delay fault testing. J. Electron. Test. 8(2): 219-222 (1996) - [j10]Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis
C-Testable modified-Booth multipliers. J. Electron. Test. 8(3): 241-260 (1996) - [j9]Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis
Testing CMOS combinational iterative logic arrays for realistic faults. Integr. 21(3): 209-228 (1996) - [c7]Dimitris Nikolos, Haridimos T. Vergos, Antonis Vazaios, Spyros Voulgaris:
Yield - Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip Caches. DFT 1996: 53-58 - [c6]Dimitris Nikolos, Haridimos T. Vergos:
On the Yield of VLSI Processors with on-chip CPU Cache. EDCC 1996: 214-230 - 1995
- [j8]Haridimos T. Vergos, Dimitris Nikolos:
Efficient fault tolerant cache memory design. Microprocess. Microprogramming 41(2): 153-169 (1995) - [j7]Vassilios V. Dimakopoulos, G. Sourtziotis, Antonis M. Paschalis
On TSC Checkers for m-out-n Codes. IEEE Trans. Computers 44(8): 1055-1059 (1995) - [j6]Th. Haniotakis, Antonis M. Paschalis
Efficient Totally Self-Checking Checkers for a Class of Borden Codes. IEEE Trans. Computers 44(11): 1318-1322 (1995) - [c5]Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis:
An efficient comparative concurrent Built-In Self-Test technique. Asian Test Symposium 1995: 309-315 - [c4]Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis:
Accumulator-based BIST approach for stuck-open and delay fault testing. ED&TC 1995: 431-437 - [c3]Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis:
Testing combinational iterative logic arrays for realistic faults. VTS 1995: 35-41 - 1992
- [j5]Dimitris Nikolos, Alexandros Krokos:
Theory and Design of t-Error Correcting, k-Error Detecting and d-Unidirectional Error Detecting Codes with d > k > t. IEEE Trans. Computers 41(4): 411-419 (1992) - 1991
- [j4]Dimitris Nikolos:
Theory and Design of t-Error Correcting/d-Error Detecting (d>t) and All Unidirectional Error Detecting Codes. IEEE Trans. Computers 40(2): 132-142 (1991)
1980 – 1989
- 1988
- [j3]Antonis M. Paschalis
Efficient Modular Design of TSC Checkers for M-out-of-2M Codes. IEEE Trans. Computers 37(3): 301-309 (1988) - [j2]Dimitris Nikolos, Antonis M. Paschalis
Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes. IEEE Trans. Computers 37(7): 807-814 (1988) - 1986
- [j1]Dimitris Nikolos, Nikolaos Gaitanis, George Philokyprou:
Systematic t-Error Correcting/All Unidirectional Error Detecting Codes. IEEE Trans. Computers 35(5): 394-402 (1986) - [c2]Antonis M. Paschalis
Efficient Modular Design of TSC Checkers for M-out-of-2M Codes. Aegean Workshop on Computing 1986: 144-155 - 1984
- [c1]Dimitris Nikolos, Nikolaos Gaitanis, George Philokyprou:
Systematic t-error correcting all unidirectional error detecting codes. Fehlertolerierende Rechensysteme 1984: 177-188
Coauthor Index
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last updated on 2024-10-07 22:12 CEST by the dblp team
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