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22nd FPL 2012: Oslo, Norway
- Dirk Koch, Satnam Singh, Jim Tørresen:
22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012. IEEE 2012, ISBN 978-1-4673-2257-7 - Michael J. Flynn, Oliver Pell, Oskar Mencer:
Dataflow supercomputing. 1-3 - Doris Chen, Deshanand P. Singh
:
Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filtering. 5-12 - Adrien Le Masle, Wayne Luk:
Detecting power attacks on reconfigurable hardware. 14-19 - Suvarna Mane, Mostafa M. I. Taha, Patrick Schaumont
Efficient and side-channel-secure block cipher implementation with custom instructions on FPGA. 20-25 - George Eichinger, Kaushik R. Chowdhury
CRUSH: Cognitive Radio Universal Software Hardware. 26-32 - Raul Torrego
Data coding functions for Software Defined Radios implemented on R3TOS. 33-40 - Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings:
EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip. 41-48 - Eddie Hung, Steven J. E. Wilton:
Limitations of incremental signal-tracing for FPGA debug. 49-56 - Florian Devic, Lionel Torres, Jérémie Crenne, Benoît Badrignans, Pascal Benoit:
SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration. 57-62 - Ken Eguro, Ramarathnam Venkatesan:
FPGAs for trusted cloud computing. 63-70 - Carl Ingemarsson, Petter Kallstrom, Oscar Gustafsson
Using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAs. 71-74 - Michael Feilen, Matthias Ihmig, Christian Schwarzbauer, Walter Stechele:
Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources. 75-82 - Niyati Shah, Jonathan Rose:
On the difficulty of pin-to-wire routing in FPGAs. 83-90 - Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip Brisk
Routing algorithms for FPGAS with sparse intra-cluster routing crossbars. 91-98 - Brahim Betkaoui, Yu Wang
Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study. 99-104 - Michael Henrey, Sean Edmond, Lesley Shannon, Carlo Menon
Bio-inspired walking: A FPGA multicore system for a legged robot. 105-111 - Graeme Coapes
A scalable FPGA-based design for field programmable large-scale ion channel simulations. 112-119 - Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto:
Scalability analysis of tightly-coupled FPGA-cluster for lattice Boltzmann computation. 120-127 - Zoltán Nagy, Csaba Nemes, Antal Hiba
FPGA based acceleration of computational fluid flow simulation on unstructured mesh geometry. 128-135 - Takayuki Akamine, Kenta Inakagata, Yasunori Osana
Reconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamics. 136-142 - Marcel Gort, Jason Helge Anderson:
Analytical placement for heterogeneous FPGAs. 143-150 - Jaren Lamprecht, Brad L. Hutchings:
Profiling FPGA floor-planning effects on timing closure. 151-156 - Aaron Wood, Adam Knight, Benjamin Ylvisaker, Scott Hauck:
Multi-kernel floorplanning for enhanced CGRAS. 157-164 - Qiwei Jin, Tobias Becker
Optimising explicit finite difference option pricing for dynamic constant reconfiguration. 165-172 - Xinyu Niu, Qiwei Jin, Wayne Luk, Qiang Liu, Oliver Pell:
Exploiting run-time reconfiguration in stencil computation. 173-180 - Rinse Wester, Christiaan Baaij, Jan Kuper:
A two step hardware design method using CλaSH. 181-188 - Björn Meyer, Jörn Schumacher
Convey vector personalities - FPGA acceleration with an openmp-like programming effort? 189-196 - Andrew Somerville, Kenneth B. Kent
Improving memory support in the VTR flow. 197-202 - Tim Todman, Wayne Luk:
Verification of streaming designs by combining symbolic simulation and equivalence checking. 203-208 - Jungwook Choi, Rob A. Rutenbar
Hardware implementation of MRF map inference on an FPGA platform. 209-216 - Atabak Mahram, Martin C. Herbordt:
CAAD BLASTP 2.0: NCBI BLASTP accelerated with pipelined filters. 217-223 - Eric Matthews, Lesley Shannon, Alexandra Fedorova:
Polyblaze: From one to many bringing the microblaze into the multicore era with Linux SMP support. 224-230 - Eugene Cartwright, Azad Fahkari, Sen Ma, Christina Smith, Miaoqing Huang, David Andrews
Automating the design of mLUT MPSoPC FPGAs in the cloud. 231-236 - Takashi Takenaka, Masamichi Takagi, Hiroaki Inoue:
A scalable complex event processing framework for combination of SQL-based continuous queries and C/C++ functions. 237-242 - Thusitha N. Chandrapala, Amila P. Cabral, Sapumal Ahangama, Thilina S. Ambagahawaththa
Hardware implementation of motion blur removal. 243-248 - Bogdan Pasca
Correctly rounded floating-point division for DSP-enabled FPGAs. 249-254 - Martin Kumm, Katharina Liebisch, Peter Zipf
Reduced complexity single and multiple constant multiplication in floating point precision. 255-261 - Alexios Balatsoukas-Stimming, Apostolos Dollas:
FPGA-based design and implementation of a multi-GBPS LDPC decoder. 262-269 - Thilan Ganegedara, Viktor K. Prasanna, Gordon J. Brebner
Optimizing packet lookup in time and space on FPGA. 270-276 - Rodrigo Bernardo, Luis R. Monte, Eduardo Mobilon, Valentino Corso, Arley H. Salvador, Carolina G. Neves, Cleber A. Nakandakare, Daniele R. da Silva, Luis P. F. de Barros, Ronaldo F. da Silva:
Architecture and FPGA implementation of a 10.7 Gbit/s OTN Regenerator for optical communication systems. 277-283 - Abdulazim Amouri, Mehdi Baradaran Tahoori:
High-level aging estimation for FPGA-mapped designs. 284-291 - Jaime Espinosa
Tolerating multiple faults with proximate manifestations in FPGA-based critical designs for harsh environments. 292-299 - Adam Jacobs, Grzegorz Cieslewski, Alan D. George
Overhead and reliability analysis of algorithm-based fault tolerance in FPGA systems. 300-306 - Fatma Abouelella, Karel Bruneel, Dirk Stroobandt:
Automatically exploiting regularity in applications to reduce reconfiguration memory requirements. 307-314 - Karel Heyse, Karel Bruneel, Dirk Stroobandt:
Mapping logic to reconfigurable FPGA routing. 315-321 - Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt:
Maximizing the reuse of routing resources in a reconfiguration-aware connection router. 322-329 - Jason Oberg, Ken Eguro, Ray Bittner, Alessandro Forin:
Random decision tree body part recognition using FPGAs. 330-337 - Izaan Allugundu, Pranay Puranik, Yat Piu Lo, Akash Kumar
Acceleration of distance-to-default with hardware-software co-design. 338-344 - Wenjuan Deng, Yiqun Zhu, Hao Feng, Zhiguo Jiang:
An efficient hardware architecture of the optimised SIFT descriptor generation. 345-352 - Robin Panda, Carl Ebeling, Scott Hauck:
Adding dataflow-driven execution control to a Coarse-Grained Reconfigurable Array. 353-360 - Takashi Yoza, Minoru Watanabe:
A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment function. 361-366 - Yi-Chung Chen, Wenhua Wang, Hai Li
Non-volatile 3D stacking RRAM-based FPGA. 367-372 - Ghaith Tarawneh
Intra-chip physical parameter sensor for FPGAS using flip-flop metastability. 373-379 - Abhranil Maiti, Patrick Schaumont
A novel microprocessor-intrinsic Physical Unclonable Function. 380-387 - Swetha Pappala, Mohammed Y. Niamat, Weiqing Sun:
FPGA based key generation technique for anti-counterfeiting methods using Physically Unclonable Functions and artificial intelligence. 388-393 - Antoni Roca, José Flich
DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS. 394-399 - Chin Hau Hoo, Akash Kumar
An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay. 400-406 - Daichi Kobori, Tsutomu Maruyama:
An acceleration of a graph cut segmentation with FPGA. 407-413 - Haruhisa Tsuyama, Tsutomu Maruyama:
An FPGA acceleration of a level set segmentation method. 414-420 - Ashwin A. Mendon, Bin Huang, Ron Sass:
A high performance, open source SATA2 core. 421-428 - Thomas P. Perry, Richard L. Walke, Rob Payne, Stefan Petko, Khaled Benkrid:
IP-XACT extensions for IP interoperability guarantees and software model generation. 429-436 - Zhongduo Lin, Charles Lo, Paul Chow:
K-means implementation on FPGA for high-dimensional data using triangle inequality. 437-442 - Abid Rafique, Nachiket Kapre
Enhancing performance of Tall-Skinny QR factorization using FPGAs. 443-450 - Chunmeng Bi, Tsutomu Maruyama:
Real-time corner and polygon detection system on FPGA. 451-457 - Keisuke Dohi, Yuma Hatanaka, Kazuhiro Negi, Yuichiro Shibata, Kiyoshi Oguri:
Deep-pipelined FPGA implementation of ellipse estimation for eye tracking. 458-463 - Jason Xin Zheng, Ethan Chen, Miodrag Potkonjak:
A Benign Hardware Trojan on FPGA-based embedded systems. 464-470 - Jeremy Abramson, Pedro C. Diniz:
A resiliency-aware scheduling approach for FPGA configuration: Preliminary results. 471-472 - Bruno de Abreu Silva, Vanderlei Bonato
Power/performance optimization in FPGA-based asymmetric multi-core systems. 473-474 - Krishna Chaitanya Nunna, Farhad Mehdipour, Kazuaki J. Murakami:
Thermal-aware partitioning for 3D FPGAs. 475-476 - Leyla S. Ghazanfari, Roberto Airoldi, Jari Nurmi
Reconfigurable multi-processor architecture for streaming applications. 477-478 - Marco Ramírez, Masoud Daneshtalab, Juha Plosila
NoC-AXI interface for FPGA-based MPSoC platforms. 479-480 - Bahram N. Uchevler, Kjetil Svarstad
Modeling of dynamic reconfigurable systems with Haskell. 481-482 - Ivan Kastelan
Stimulation board for automated verification of touchscreen-based devices. 483-484 - Anja Niedermeier, Jan Kuper, Gerard J. M. Smit:
High level structural description of streaming applications. 485-486 - Milica Orlandic
Ambient hardware and the case for transcoding media streams. 487-488 - Cristiano B. Oliveira, Eduardo Marques
Combining data and computation transformations for fine-grain reconfigurable architectures. 489-490 - D. Erdenechimeg, Ts. Sugir, François Philipp, Manfred Glesner:
Implementation and outcomes of FPGA-based system design in Mongolian education. 491-494 - Chao Wang, Xi Li, Junneng Zhang, Peng Chen, Xuehai Zhou:
CaaS: Core as a service realizing hardware sercices on reconfigurable MPSoCS. 495-498 - Junichi Sawada, Hiroaki Nishi
Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism. 499-502 - Sharad Sinha
Dataflow graph partitioning for high level synthesis. 503-506 - Minxi Jin, Tsutomu Maruyama:
A fast and high quality stereo matching algorithm on FPGA. 507-510 - Yupeng Chen, Bertil Schmidt
An FPGA aligner for short read mapping. 511-514 - Marc-André Daigneault, Jean-Pierre David:
Raising the abstraction level of HDL for control-dominant applications. 515-518 - Zhenyu Guan, Justin S. J. Wong
A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. 519-522 - Ray Bittner:
Speedy bus mastering PCI express. 523-526 - Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung, Alison Eele, Jan M. Maciejowski:
Adaptive Sequential Monte Carlo approach for real-time applications. 527-530 - Tomasz S. Czajkowski, Utku Aydonat, Dmitry Denisenko, John Freeman, Michael Kinsner, David Neto, Jason Wong, Peter Yiannacouras, Deshanand P. Singh:
From opencl to high-performance hardware on FPGAS. 531-534 - Stefan Wallentowitz
A framework for Open Tiled Manycore System-On-Chip. 535-538 - Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Fault detection and avoidance of FPGA in various granularities. 539-542 - Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. 543-546 - Rubén Salvador
Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. 547-550 - Kanav Khurana, Pooja Gupta, Rajesh Chandrasekhara Panicker, Akash Kumar
Development of an FPGA-based real-time P300 speller. 551-554 - Christian Hochberger, Changgong Li, Michael Raitza, Markus Vogt:
Influence of operating conditions on ring oscillator-based entropy sources in FPGAs. 555-558 - Christoph Ruething, Andreas Agne, Markus Happe
Exploration of ring oscillator design space for temperature measurements on FPGAs. 559-562 - Changqing Xun, Mei Wen, Nan Wu, Chunyuan Zhang, Hayden Kwok-Hay So
Extending BORPH for shared memory reconfigurable computers. 563-566 - David Sheffield, Michael J. Anderson, Kurt Keutzer:
Automatic generation of application-specific accelerators for FPGAs from python loop nests. 567-570 - Tassadaq Hussain, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé
PPMC: Hardware scheduling and memory management support for multi accelerators. 571-574 - Amila Akagic
Performance analysis of fully-adaptable CRC accelerators on an FPGA. 575-578 - Daniel Llamocca
Dynamic multiobjective optimization management of the Energy-Performance-Accuracy space for separable 2-D complex filters. 579-582 - Yan Xu, Olivier Muller, Pierre-Henri Horrein, Frédéric Pétrot:
HCM: An abstraction layer for seamless programming of DPR FPGA. 583-586 - Adam Powell, Christos-Savvas Bouganis
Early performance estimation of image compression methods on soft processors. 587-590 - Michael Kunz, Martin Kumm, Martin Heide, Peter Zipf
Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system. 591-594 - Mário P. Véstias
Sliding block Viterbi decoders in FPGA. 595-598 - Masamichi Takagi, Takashi Takenaka, Hiroaki Inoue:
Dynamic query switching for complex event processing on FPGAs. 599-602 - Joaquín Olivares
Dual-core motion estimation processor. 603-606 - Christian Pilato
On the automatic integration of hardware accelerators into FPGA-based embedded systems. 607-610 - Hemant Balijepalli, Mohammed Y. Niamat:
Design of a novel Quantum-dot Cellular Automata Field Programmable Gate Array. 611-614 - Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto
A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture. 615-618 - Razvan Nane
DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler. 619-622 - Junfeng Chu, Mohammed Benaissa:
Low area memory-free FPGA implementation of the AES algorithm. 623-626 - Hanaa M. Hussain, Khaled Benkrid, Chuan Hong, Huseyin Seker:
An adaptive FPGA implementation of multi-core K-nearest neighbour ensemble classifier using dynamic partial reconfiguration. 627-630 - Sam Collinson, John Morris:
Fast digital rendering for special effects. 631-634 - Scott Buscemi, Ron Sass:
Design and utilization of an FPGA cluster to implement a Digital Wireless Channel Emulator. 635-638 - Kazuhiko Terada, Hiroyuki Uzawa, Namiko Ikeda, Satoshi Shigematsu, Nobuyuki Tanaka, Masami Urano:
Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs. 639-642 - Paulo Da Cunha Possa, Sidi Ahmed Mahmoudi
A new self-adapting architecture for feature detection. 643-646 - Alok Prakash, Christopher T. Clarke, Thambipillai Srikanthan:
Custom instructions with local memory elements without expensive DMA transfers. 647-650 - José M. Granado Criado
Dual MicroBlaze rekeying processor for group key management. 651-654 - Pascal Cotret, Guy Gogniat
Lightweight reconfiguration security services for AXI-based MPSoCs. 655-658 - Di Wang, Christopher T. Clarke, A. N. Evans:
Examination of the concept of a row-column separated median filter. 659-662 - Robert Beat, Philipp Grabher, Daniel Page, Stefan Tillich, Marcin Wójcik:
On reconfigurable fabrics and generic side-channel countermeasures. 663-666 - George Lentaris, Dionysios Diamantopoulos, Kostas Siozios
Hardware implementation of stereo correspondence algorithm for the ExoMars mission. 667-670 - Davy Wolfs, Kris Aerts
Design space exploration for automatically generated cryptographic hardware using functional languages. 671-674 - Uli Kretzschmar, Armando Astarloa
Fast and accurate Single Bit Error injection into SRAM Based FPGAs. 675-678 - François Philipp, Manfred Glesner:
(GECO)2: A graphical tool for the generation of configuration bitstreams for a smart sensor interface based on a Coarse-Grained Dynamically Reconfigurable Architecture. 679-682 - Chuan Hong, Khaled Benkrid, Xabier Iturbe
Design and implementation of fault-tolerant soft processors on FPGAs. 683-686 - Gerald Hempel, Christian Hochberger, Michael Raitza:
Towards GCC-based automatic soft-core customization. 687-690 - Shadi Traboulsi, Wenlong Zhang, David Szczesny, Anas Showk, Attila Bilgic:
An energy-efficient hardware accelerator for Robust Header Compression in LTE-Advanced terminals. 691-694 - Gordon Inggs
Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA. 695-698 - Fuxing Zhang, Yingke Xie, Junjie Liu, Layong Luo, Qingsong Ning, Xiaolong Wu:
ITester: A FPGA based high performance traffic replay tool. 699-702 - Sébastien Guillet, Florent de Lamotte, Nicolas Le Griguer, Éric Rutten, Jean-Philippe Diguet, Guy Gogniat
Modeling and synthesis of a Dynamic and Partial Reconfiguration controller. 703-706 - Alessandra Bonetto, Andrea Cazzaniga, Gianluca Durelli, Christian Pilato
An open-source design and validation platform for reconfigurable systems. 707-710 - Mateusz Komorkiewicz, Maciej Kluczewski, Marek Gorgon:
Floating point HOG implementation for real-time multiple object detection. 711-714 - Travis Manderson, Laurence Turner:
Runtime reconfigurable DSP unit using one's complement and Minimum Signed Digit. 715-718 - Ercan Kalali
A high performance and low energy intra prediction hardware for High Efficiency Video Coding. 719-722 - Rui Policarpo Duarte, Christos-Savvas Bouganis
High-level linear projection circuit design optimization framework for FPGAs under over-clocking. 723-726 - Bajaj Ronak, Suhaib A. Fahmy
Evaluating the efficiency of DSP Block synthesis inference from flow graphs. 727-730 - Christian Köllner, Nico Adler, Klaus D. Müller-Glaser:
System#: High-level synthesis of physical simulations for FPGA-based real-time execution. 731-734 - Florian Benz, André Seffrin, Sorin A. Huss:
Bil: A tool-chain for bitstream reverse-engineering. 735-738 - Dang Ba Khac Trieu, Tsutomu Maruyama:
A region merging approach for image segmentation on FPGA. 739-742 - Petr Pfeifer
On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults. 743-746 - Maria Kalenderi, Dionisios N. Pnevmatikatos
Breaking the GSM A5/1 cryptography algorithm with rainbow tables and high-end FPGAS. 747-753
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