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Terrence S. T. Mak
Sui-Tung Mak
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- affiliation: University of Southampton, UK
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2020 – today
- 2022
- [j51]Ammar Karkar, Nizar Dahir
, Terrence S. T. Mak, Kin-Fai Tong:
Thermal and Performance Efficient On-Chip Surface-Wave Communication for Many-Core Systems in Dark Silicon Era. ACM J. Emerg. Technol. Comput. Syst. 18(3): 49:1-49:18 (2022) - 2021
- [j50]Weilong Chen, Xiaohang Wang
Evolution of Publications, Subjects, and Co-Authorships in Network-on-Chip Research From a Complex Network Perspective. IEEE Access 9: 149399-149422 (2021) - [j49]Nizar Dahir
Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach. Integr. 81: 342-353 (2021) - [j48]Siyuan Xiao, Xiaohang Wang
On Performance Optimization and Quality Control for Approximate-Communication-Enabled Networks-on-Chip. IEEE Trans. Computers 70(11): 1817-1830 (2021) - [j47]Weidong Gao
Molecular Type Spread Molecular Shift Keying for Multiple-Access Diffusive Molecular Communications. IEEE Trans. Mol. Biol. Multi Scale Commun. 7(1): 51-63 (2021) - 2020
- [j46]Yiming Zhao
On hardware-trojan-assisted power budgeting system attack targeting many core systems. J. Syst. Archit. 109: 101757 (2020) - [j45]Benjamin J. Fletcher
A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration. IEEE J. Solid State Circuits 55(9): 2414-2428 (2020) - [j44]Libo Qian
A Fast-Transient Response Digital Low-Dropout Regulator With Dual-Modes Tuning Technique. IEEE Trans. Circuits Syst. 67-II(12): 2943-2947 (2020) - [j43]Qian Ding
An Active Silicon Interposer With Low-Power Hybrid Wireless-Wired Clock Distribution Network for Many-Core Systems. IEEE Trans. Very Large Scale Integr. Syst. 28(9): 2042-2054 (2020) - [c80]Benjamin J. Fletcher, Terrence S. T. Mak, Shidhartha Das:
A 3D-Stacked Cortex-M0 SoC with 20.3Gbps/mm2 7.1mW/mm2 Simultaneous Wireless Inter-Tier Data and Power Transfer. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j42]Liang Wang
A Non-Minimal Routing Algorithm for Aging Mitigation in 2D-Mesh NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1373-1377 (2019) - [j41]Liang Wang
A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1771-1784 (2019) - [j40]Bing Li, Xiaohang Wang
On Runtime Communication and Thermal-Aware Application Mapping and Defragmentation in 3D NoC Systems. IEEE Trans. Parallel Distributed Syst. 30(12): 2775-2789 (2019) - [j39]Benjamin J. Fletcher
Design and Optimization of Inductive-Coupling Links for 3-D-ICs. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 711-723 (2019) - [c79]Siyuan Xiao, Xiaohang Wang, Maurizio Palesi, Amit Kumar Singh, Terrence S. T. Mak:
ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip. DATE 2019: 630-633 - [c78]Benjamin J. Fletcher
CoDAPT: A Concurrent Data And Power Transceiver for Fully Wireless 3D-ICs. DATE 2019: 1343-1348 - [c77]Benjamin J. Fletcher
A 10.8pJ/bit Pulse-Position Inductive Transceiver for Low-Energy Wireless 3D Integration. ESSCIRC 2019: 121-124 - [c76]Weidong Gao
Type-Spread Molecular Communications: Principles and Inter-Symbol Interference Mitigation. ICC 2019: 1-6 - [c75]Benjamin J. Fletcher
A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration. ISLPED 2019: 1-6 - [e3]Tom J. Kazmierski, Reinhard von Hanxleden, Terrence S. T. Mak:
2019 Forum for Specification and Design Languages, FDL 2019, Southampton, United Kingdom, September 2-4, 2019. IEEE 2019, ISBN 978-1-7281-4113-8 [contents] - 2018
- [j38]Yee Leung, Kwong-Sak Leung, Man Hon Wong, Terrence S. T. Mak
An integrated web-based air pollution decision support system - a prototype. Int. J. Geogr. Inf. Sci. 32(9): 1787-1814 (2018) - [j37]Kin Ming Lo, Wei Ying Yi, Pak-Kan Wong, Kwong-Sak Leung, Yee Leung, Sui-Tung Mak:
A Genetic Algorithm with New Local Operators for Multiple Traveling Salesman Problems. Int. J. Comput. Intell. Syst. 11(1): 692-705 (2018) - [j36]Ling Wang
A Fault-Tolerant Routing Algorithm Using Tunnels in Fault Blocks for Network-on-Chip. J. Circuits Syst. Comput. 27(2): 1850022:1-1850022:11 (2018) - [j35]Li Zhang, Xiaohang Wang, Yingtao Jiang, Mei Yang, Terrence S. T. Mak, Amit Kumar Singh:
Effectiveness of HT-assisted sinkhole and blackhole denial of service attacks targeting mesh networks-on-chip. J. Syst. Archit. 89: 84-94 (2018) - [j34]Shufan Yang
A neuro-inspired visual tracking method based on programmable system-on-chip platform. Neural Comput. Appl. 30(9): 2697-2708 (2018) - [j33]Xiaohang Wang, Amit Kumar Singh
Bubble Budgeting: Throughput Optimization for Dynamic Workloads by Exploiting Dark Cores in Many Core Systems. IEEE Trans. Computers 67(2): 178-192 (2018) - [j32]Ammar Karkar
Network-on-Chip Multicast Architectures Using Hybrid Wire and Surface-Wave Interconnects. IEEE Trans. Emerg. Top. Comput. 6(3): 357-369 (2018) - [c74]Benjamin J. Fletcher
A high-speed design methodology for inductive coupling links in 3D-ICs. DATE 2018: 497-502 - [c73]Benjamin J. Fletcher
Low-power 3D integration using inductive coupling links for neurotechnology applications. DATE 2018: 1211-1216 - [c72]Zijun Long, Xiaohang Wang, Yingtao Jiang, Guofeng Cui, Li Zhang, Terrence S. T. Mak:
Improving the efficiency of thermal covert channels in multi-/many-core systems. DATE 2018: 1459-1464 - [c71]Qian Ding, Benjamin J. Fletcher, Terrence S. T. Mak:
Globally Wireless Locally Wired (GloWiLoW): A Clock Distribution Network for Many-Core Systems. ISCAS 2018: 1-5 - [c70]Yiming Zhao, Xiaohang Wang, Yingtao Jiang, Mei Yang, Amit Kumar Singh, Terrence S. T. Mak:
On a New Hardware Trojan Attack on Power Budgeting of Many Core Systems. SoCC 2018: 1-6 - [c69]Terrence S. T. Mak, Hiroki Matsutani, Partha Pratim Pande:
Special session on bringing cores closer together: The wireless revolution in on-chip communication. VTS 2018: 1 - 2017
- [j31]Xiaohang Wang, Yingtao Jiang, Mei Yang, Hong Li, Terrence S. T. Mak:
HRC: A 3D NoC Architecture with Genuine Support for Runtime Thermal-Aware Task Management. IEEE Trans. Computers 66(10): 1676-1688 (2017) - [j30]Michael Opoku Agyeman
A Resilient 2-D Waveguide Communication Fabric for Hybrid Wired-Wireless NoC Design. IEEE Trans. Parallel Distributed Syst. 28(2): 359-373 (2017) - [c68]Liang Wang
Runtime task mapping for lifetime budgeting in many-core systems. FDL 2017: 1-8 - [c67]Liang Wang
Throughput Optimization for Lifetime Budgeting in Many-Core Systems. ACM Great Lakes Symposium on VLSI 2017: 451-454 - [c66]Bing Li, Xiaohang Wang, Amit Kumar Singh, Terrence S. T. Mak:
On Runtime Communication- and Thermal-aware Application Mapping in 3D NoC. NOCS 2017: 16:1-16:8 - [i1]Quoc-Tuan Vien, Michael Opoku Agyeman, Tuan Anh Le, Terrence S. T. Mak:
On the Nanocommunications at THz Band in Graphene-Enabled Wireless Network-on-Chip. CoRR abs/1708.06209 (2017) - 2016
- [j29]Ra'ed Al-Dujaily, An Li, Robert G. Maunder
A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation. IEEE Access 4: 9880-9894 (2016) - [j28]Xiaohang Wang, Baoxin Zhao, Ling Wang, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab
A pareto-optimal runtime power budgeting scheme for many-core systems. Microprocess. Microsystems 46: 136-148 (2016) - [j27]Xiaohang Wang, Ting Fei, Boquan Zhang, Terrence S. T. Mak:
On runtime adaptive tile defragmentation for resource management in many-core systems. Microprocess. Microsystems 46: 161-174 (2016) - [j26]Junwen Luo, Graeme Coapes
Real-Time Simulation of Passage-of-Time Encoding in Cerebellum Using a Scalable FPGA-Based System. IEEE Trans. Biomed. Circuits Syst. 10(3): 742-753 (2016) - [j25]Xiaohang Wang, Baoxin Zhao, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab
On Fine-Grained Runtime Power Budgeting for Networks-on-Chip Systems. IEEE Trans. Computers 65(9): 2780-2793 (2016) - [j24]Liang Wang
Adaptive Routing Algorithms for Lifetime Reliability Optimization in Network-on-Chip. IEEE Trans. Computers 65(9): 2896-2902 (2016) - [j23]Qiang Liu, Wenqing Ji, Qi Chen, Terrence S. T. Mak:
IP Protection of Mesh NoCs Using Square Spiral Routing. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1560-1573 (2016) - [j22]Jim Ng, Xiaohang Wang, Amit Kumar Singh, Terrence S. T. Mak:
Defragmentation for Efficient Runtime Resource Management in NoC-Based Many-Core Systems. IEEE Trans. Very Large Scale Integr. Syst. 24(11): 3359-3372 (2016) - [c65]Michael Opoku Agyeman
An Analytical Channel Model for Emerging Wireless Networks-on-Chip. CSE/EUC/DCABES 2016: 9-15 - [c64]Wei-Ying Yi, Kwong-Sak Leung, Yee Leung, Helen Mei-Ling Meng, Terrence S. T. Mak:
Modular sensor system (MSS) for urban air pollution monitoring. IEEE SENSORS 2016: 1-3 - [c63]Xiaohang Wang, Amit Kumar Singh, Bing Li, Yang Yang, Terrence S. T. Mak, Hong Li:
Bubble budgeting: throughput optimization for dynamic workloads by exploiting dark cores in many core systems. NOCS 2016: 1-8 - [c62]Michael Opoku Agyeman
An Efficient Channel Model for Evaluating Wireless NoC Architectures. SBAC-PAD (Workshops) 2016: 85-90 - 2015
- [j21]Masoud Daneshtalab
Introduction to the special issue on NoC-based many-core architectures. Comput. Electr. Eng. 45: 359-361 (2015) - [j20]Xiaohang Wang, Baoxin Zhao, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab
An efficient runtime power allocation scheme for many-core systems inspired from auction theory. Integr. 50: 147-157 (2015) - [j19]Wei Ying Yi
A Survey of Wireless Sensor Network Based Air Pollution Monitoring Systems. Sensors 15(12): 31392-31427 (2015) - [j18]Qiang Liu, Terrence S. T. Mak, Tao Zhang, Xinyu Niu, Wayne Luk, Alex Yakovlev
Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1402-1414 (2015) - [c61]Xiaohang Wang, Tengfei Wang, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab:
Fine-grained runtime power budgeting for networks-on-chip. ASP-DAC 2015: 160-165 - [c60]Ammar Karkar, Kin-Fai Tong, Terrence S. T. Mak, Alexandre Yakovlev:
Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting. DATE 2015: 794-799 - [c59]Michael Opoku Agyeman
Towards reliability and performance-aware Wireless Network-on-Chip design. DFTS 2015: 205-210 - [c58]Michael Opoku Agyeman
An Improved Wireless Communication Fabric for Emerging Network-on-Chip Design. FNC/MobiSPC 2015: 415-420 - [c57]Michael Opoku Agyeman
On the Design of Reliable Hybrid Wired-Wireless Network-on-Chip Architectures. MCSoC 2015: 251-258 - [c56]Wen Zong, Michael Opoku Agyeman
Unbiased Regional Congestion Aware Selection Function for NoCs. NOCS 2015: 19:1-19:8 - [c55]Michael Opoku Agyeman
Novel Hybrid Wired-Wireless Network-on-Chip Architectures: Transducer and Communication Fabric Design. NOCS 2015: 32:1-32:2 - [c54]Jim Ng, Xiaohang Wang, Amit Kumar Singh, Terrence S. T. Mak:
DeFrag: Defragmentation for Efficient Runtime Resource Allocation in NoC-Based Many-core Systems. PDP 2015: 345-352 - 2014
- [j17]Masoud Daneshtalab
Introduction to the Special Issue on Network-on-Chip Architectures. Comput. Electr. Eng. 40(8): 257-259 (2014) - [j16]Nizar Dahir
Modeling and Tools for Power Supply Variations Analysis in Networks-on-Chip. IEEE Trans. Computers 63(3): 679-690 (2014) - [j15]Xiaohang Wang, Mei Yang, Yingtao Jiang, Peng Liu, Masoud Daneshtalab
On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. ACM Trans. Embed. Comput. Syst. 13(2s): 73:1-73:21 (2014) - [j14]Nizar Dahir
Thermal Optimization in Network-on-Chip-Based 3D Chip Multiprocessors Using Dynamic Programming Networks. ACM Trans. Embed. Comput. Syst. 13(4s): 139:1-139:25 (2014) - [j13]Ghaith Tarawneh
Eliminating Synchronization Latency Using Sequenced Latching. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 408-419 (2014) - [c53]Xiaohang Wang, Zhiming Li, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Terrence S. T. Mak:
Agile frequency scaling for adaptive power allocation in many-core systems powered by renewable energy sources. ASP-DAC 2014: 298-303 - [c52]Ammar Karkar, Nizar Dahir, Ra'ed Al-Dujaily, Kenneth Tong, Terrence S. T. Mak, Alex Yakovlev:
Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip. DATE 2014: 1-4 - [c51]Xiaohang Wang, Baoxin Zhao, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi:
Adaptive power allocation for many-core systems inspired from multiagent auction model. DATE 2014: 1-4 - [c50]Junwen Luo, Graeme Coapes
A scalable FPGA-based cerebellum for passage-of-time representation. EMBC 2014: 3102-3105 - [c49]Wing Oi Siu, Terrence S. T. Mak:
Intra- and inter-chip voltage droop analysis using a power delivery grid model. ISIC 2014: 208-211 - [c48]Junwen Luo, Graeme Coapes
A real-time silicon cerebellum spiking neural model based on FPGA. ISIC 2014: 276-279 - [c47]Jim Ng, Terrence S. T. Mak:
A Novel Partitioning Algorithm for Optimizing Neuron-to-Neuron Pathways through NoC in BMI. NoCArc@MICRO 2014: 57-62 - [c46]Nizar Dahir
Design and Implementation of Dynamic Thermal-Adaptive Routing Strategy for Networks-on-Chip. PDP 2014: 384-391 - [c45]Liang Wang, Xiaohang Wang, Terrence S. T. Mak:
Dynamic programming-based lifetime aware adaptive routing algorithm for Network-on-Chip. VLSI-SoC 2014: 1-6 - [c44]Liang Wang
Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip. VLSI-SoC (Selected Papers) 2014: 1-20 - 2013
- [j12]Ra'ed Al-Dujaily, Terrence S. T. Mak, Kai-Pui Lam, Fei Xia, Alex Yakovlev
Dynamic On-Chip Thermal Optimization for Three-Dimensional Networks-On-Chip. Comput. J. 56(6): 756-770 (2013) - [j11]Nizar Dahir
Highly adaptive and deadlock-free routing for three-dimensional networks-on-chip. IET Comput. Digit. Tech. 7(6): 255-263 (2013) - [j10]Ammar Karkar
Hybrid wire-surface wave interconnects for next-generation networks-on-chip. IET Comput. Digit. Tech. 7(6): 294-303 (2013) - [j9]Xiaohang Wang, Mei Yang, Yingtao Jiang, Maurizio Palesi, Peng Liu, Terrence S. T. Mak, Nader Bagherzadeh
Efficient multicast schemes for 3-D Networks-on-Chip. J. Syst. Archit. 59(9): 693-708 (2013) - [j8]Bo Yu, Rosa H. M. Chan, Terrence S. T. Mak, Yihe Sun, Chi-Sang Poon:
On-Chip Systolic Networks for Real-Time Tracking of Pairwise Correlations Between Neurons in a Large-Scale Network. IEEE Trans. Biomed. Eng. 60(1): 198-202 (2013) - [j7]Ra'ed Al-Dujaily, Nizar Dahir
Dynamic programming-based runtime thermal management (DPRTM): An online thermal control strategy for 3D-NoC systems. ACM Trans. Design Autom. Electr. Syst. 19(1): 2:1-2:27 (2013) - [c43]Athanasios K. Grivas, Terrence S. T. Mak, Alex Yakovlev
Novel Multi-Layer Network Decomposition boosting acceleration of multi-core algorithms. ASAP 2013: 249-252 - [c42]Junshi Wang, Xiaohang Wang, Letian Huang, Terrence S. T. Mak, Guangjun Li:
A Fault-Tolerant Routing Algorithm for NoC Using Farthest Reachable Routers. DASC 2013: 153-158 - [c41]Xiaohang Wang, Zhiming Li, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Terrence S. T. Mak:
A low cost, high performance dynamic-programming-based adaptive power allocation scheme for many-core architectures in the dark silicon era. ESTIMedia 2013: 61-67 - [c40]Junwen Luo, Patrick Degenaar
Towards reliable hybrid bio-silicon integration using novel adaptive control system. ISCAS 2013: 2311-2314 - [c39]Wen Zong, Xiaohang Wang, Terrence S. T. Mak:
On multicast for dynamic and irregular on-chip networks using dynamic programming method. NoCArc@MICRO 2013: 17-22 - [c38]Xiaohang Wang, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi:
On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. NOCS 2013: 1-8 - [e2]Maurizio Palesi, Terrence S. T. Mak, Masoud Daneshtalab:
Network on Chip Architectures, NoCArc '13, in conjunction with the 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7, 2013. ACM 2013, ISBN 978-1-4503-2370-3 [contents] - 2012
- [j6]Terrence S. T. Mak:
Truncation error analysis of MTBF computation for multi-latch synchronizers. Microelectron. J. 43(2): 160-163 (2012) - [j5]Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alex Yakovlev
Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip. IEEE Trans. Parallel Distributed Syst. 23(7): 1205-1215 (2012) - [c37]Andrew Mundy, Terrence S. T. Mak, Alex Yakovlev
Large-Scale On-Chip Dynamic Programming Network Inferences Using Moderated Inter-core Communication. ACSD 2012: 62-71 - [c36]Nizar Dahir
Minimizing power supply noise through harmonic mappings in networks-on-chip. CODES+ISSS 2012: 113-122 - [c35]Graeme Coapes
A scalable FPGA-based design for field programmable large-scale ion channel simulations. FPL 2012: 112-119 - [c34]Ghaith Tarawneh
Intra-chip physical parameter sensor for FPGAS using flip-flop metastability. FPL 2012: 373-379 - [c33]Ammar Karkar
Surface wave communication system for on-chip and off-chip interconnects. NoCArc@MICRO 2012: 11-16 - [c32]Nizar Dahir
Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip. NoCArc@MICRO 2012: 31-36 - [e1]Maurizio Palesi, Terrence S. T. Mak:
Fifth International Workshop on Network on Chip Architectures, NoCArc '12, Vancouver, BC, Canada, December 1, 2012. ACM 2012, ISBN 978-1-4503-1540-1 [contents] - 2011
- [j4]Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev
Real-Time FPGA-Based Multichannel Spike Sorting Using Hebbian Eigenfilters. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(4): 502-515 (2011) - [j3]Terrence S. T. Mak, Peter Y. K. Cheung, Kai-Pui Lam, Wayne Luk:
Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network. IEEE Trans. Ind. Electron. 58(8): 3701-3716 (2011) - [c31]Yu Zhou, Terrence S. T. Mak, Alex Yakovlev
Run-Time Concurrency Tuning for Peak Power Modulation in Energy Harvesting Systems. ACSD 2011: 67-76 - [c30]Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alexandre Yakovlev, Maurizio Palesi:
Run-time deadlock detection in networks-on-chip using coupled transitive closure networks. DATE 2011: 497-502 - [c29]Yu Li, Terrence S. T. Mak, Alex Yakovlev:
Redressing timing issues for speed-independent circuits in deep submicron age. DATE 2011: 1376-1381 - [c28]Bo Yu, Terrence S. T. Mak, Leslie Smith
Memory efficient on-line streaming for multichannel spike train analysis. EMBC 2011: 2315-2318 - [c27]Allann Al-armaghany, Bo Yu, Terrence S. T. Mak, Kin-Fai Tong
Feasibility study for future implantable neural-silicon interface devices. EMBC 2011: 3009-3015 - [c26]Junwen Luo, Terrence S. T. Mak, Bo Yu, Peter Andras
Towards neuro-silicon interface using reconfigurable dynamic clamping. EMBC 2011: 6389-6392 - [c25]Bo Yu, Terrence S. T. Mak, Yihe Sun, Chi-Sang Poon:
Real-time neuronal networks reconstruction using hierarchical systolic arrays. EMBC 2011: 7298-7301 - [c24]Qiang Liu, Terrence S. T. Mak, Junwen Luo, Wayne Luk, Alexandre Yakovlev
Power adaptive computing system design in energy harvesting environment. ICSAMOS 2011: 33-40 - [c23]Ra'ed Al-Dujaily, Terrence S. T. Mak, Kuan Zhou, Kai-Pui Lam, Yicong Meng, Alexandre Yakovlev
On-chip dynamic programming networks using 3D-TSV integration. ICSAMOS 2011: 318-325 - [c22]Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon:
Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC. VLSI-SoC 2011: 98-101 - [c21]Nizar Dahir
Communication centric on-chip power grid models for networks-on-chip. VLSI-SoC 2011: 180-183 - [c20]Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon:
Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network. VLSI-SoC 2011: 354-358 - 2010
- [j2]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Wave-pipelined intra-chip signaling for on-FPGA communications. Integr. 43(2): 188-201 (2010) - [j1]Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon:
A CMOS Current-Mode Dynamic Programming Circuit. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(12): 3112-3123 (2010) - [c19]Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev
A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis. FPL 2010: 556-561
2000 – 2009
- 2009
- [c18]Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam:
A DP-network for optimal dynamic routing in network-on-chip. CODES+ISSS 2009: 119-128 - [c17]Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung:
Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing. ISCAS 2009: 1293-1296 - 2008
- [c16]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
High-throughput interconnect wave-pipelining for global communication in FPGAs. FPGA 2008: 258 - [c15]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Wave-pipelined signaling for on-FPGA communication. FPT 2008: 9-16 - [c14]Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk:
Implementation of Wave-Pipelined Interconnects in FPGAs. NOCS 2008: 213-214 - [c13]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Interconnection lengths and delays estimation for communication links in FPGAs. SLIP 2008: 1-10 - [c12]Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk:
Global interconnections in FPGAs: modeling and performance analysis. SLIP 2008: 51-58 - 2007
- [c11]Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon:
A Current-Mode Analog Circuit for Reinforcement Learning Problems. ISCAS 2007: 1301-1304 - [c10]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam:
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. NOCS 2007: 173-182 - 2006
- [c9]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
On-FPGA Communication Architectures and Design Factors. FPL 2006: 1-8 - 2004
- [c8]Terrence S. T. Mak, Kai-Pui Lam:
Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA. CSB 2004: 512-514 - [c7]Terrence S. T. Mak, Kai-Pui Lam:
FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation. FPL 2004: 1076-1079 - [c6]Terrence S. T. Mak, Kai-Pui Lam:
On Computing Maximum Likelihood Phylogeny Using FPGA p. FPL 2004: 1188 - 2003
- [c5]Terrence S. T. Mak, Kai-Pui Lam:
High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign. CSB 2003: 470-473 - [c4]Kai-Pui Lam, Sui-Tung Mak:
An FPGA-based eigenfilter using fast Hebbian learning. ICASSP (2) 2003: 765-768 - [c3]H. S. Ng, Sui-Tung Mak, Kai-Pui Lam:
Field programmable gate arrays and analog implementation of BRIN for optimization problems. ISCAS (5) 2003: 73-76 - 2002
- [c2]Kai-Pui Lam, Sui-Tung Mak:
On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach. FPL 2002: 935-944 - [c1]Sui-Tung Mak, Kai-Pui Lam:
Serial-parallel tradeoff analysis of all-pairs shortest path algorithms in reconfigurable computing. FPT 2002: 302-305
Coauthor Index
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last updated on 2024-11-14 00:54 CET by the dblp team
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