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Nan Wu 0003
Person information
- affiliation: National University of Defense Technology, Changsha
Other persons with the same name
- Nan Wu — disambiguation page
- Nan Wu 0001 — Dalian Maritime University, Liaoning, China (and 1 more)
- Nan Wu 0002
— Beijing Institute of Technology, School of Information and Electronics, China
- Nan Wu 0004 — Wangfang College of Science & Technology, Henan Polytechnic University, Jiaozuo, China
- Nan Wu 0005 — New Jersey Institute of Technology, USA
- Nan Wu 0006 — Tsinghua University, Beijing, China
- Nan Wu 0007
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2010 – 2019
- 2019
- [c33]Yang Shi, Jiawei Fei, Mei Wen, Qun Huang, Nan Wu:
Metaflow: A Better Traffic Abstraction for Distributed Applications. HPCC/SmartCity/DSS 2019: 1123-1130 - 2015
- [j10]Dafei Huang, Changqing Xun, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai, Qianming Yang:
Enabling a Uniform OpenCL Device View for Heterogeneous Platforms. IEICE Trans. Inf. Syst. 98-D(4): 812-823 (2015) - [j9]Jun Chai, Johan Hake, Nan Wu, Mei Wen, Xing Cai
Towards simulation of subcellular calcium dynamics at nanometre resolution. Int. J. High Perform. Comput. Appl. 29(1): 51-63 (2015) - [j8]Johannes Langguth
Parallel performance modeling of irregular applications in cell-centered finite volume methods over unstructured tetrahedral meshes. J. Parallel Distributed Comput. 76: 120-131 (2015) - 2014
- [j7]Mei Wen, Huayou Su, Wenjie Wei, Nan Wu, Xing Cai
High efficient sedimentary basin simulations on hybrid CPU-GPU clusters. Clust. Comput. 17(2): 359-369 (2014) - [c32]Dafei Huang, Mei Wen, Changqing Xun, Dong Chen, Xing Cai
Automated Transformation of GPU-Specific OpenCL Kernels Targeting Performance Portability on Multi-Core/Many-Core CPUs. Euro-Par 2014: 210-221 - [c31]Xinnan Dong, Jun Chai, Jing Yang, Mei Wen, Nan Wu, Xing Cai
Utilizing Multiple Xeon Phi Coprocessors on One Compute Node. ICA3PP (2) 2014: 68-81 - 2013
- [j6]Jun Chai, Mei Wen, Nan Wu, Dafei Huang, Jing Yang, Xing Cai
Simulating Cardiac Electrophysiology in the Era of GPU-Cluster Computing. IEICE Trans. Inf. Syst. 96-D(12): 2587-2595 (2013) - [j5]Qianming Yang, Mei Wen, Nan Wu, Chunyuan Zhang:
Accelerating thread-intensive and explicit memory management programs with dynamic partial reconfiguration. J. Supercomput. 63(2): 508-537 (2013) - [j4]Jun Chai, Huayou Su, Mei Wen, Xing Cai
Resource-efficient utilization of CPU/GPU-based heterogeneous supercomputers for Bayesian phylogenetic inference. J. Supercomput. 66(1): 364-380 (2013) - [c30]Nan Wu, Yuran Qiao, Mei Wen, Chunyuan Zhang:
ACF: Networks-on-Chip Deadlock Recovery with Accurate Detection and Elastic Credit. APPT 2013: 319-333 - [c29]Jing Yang, Jun Chai, Mei Wen, Nan Wu, Chunyuan Zhang:
Solving the Cardiac Model Using Multi-core CPU and Many Integrated Cores (MIC). HPCC/EUC 2013: 1009-1015 - [c28]Huayou Su, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai
Performance of Sediment Transport Simulations on NVIDIA's Kepler Architecture. ICCS 2013: 1275-1281 - [c27]Huayou Su, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai
On the GPU-CPU Performance Portability of OpenCL for 3D Stencil Computations. ICPADS 2013: 78-85 - [c26]Johannes Langguth, Nan Wu, Jun Chai, Xing Cai
On the GPU performance of cell-centered finite volume method over unstructured tetrahedral meshes. IA3@SC 2013: 7:1-7:8 - [c25]Huayou Su, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai
On the GPU Performance of 3D Stencil Computations Implemented in OpenCL. ISC 2013: 125-135 - 2012
- [c24]Mei Wen, Huayou Su, Wenjie Wei, Nan Wu, Xing Cai
Using 1000+ GPUs and 10000+ CPUs for Sedimentary Basin Simulations. CLUSTER 2012: 27-35 - [c23]Mei Wen, Nan Wu, Qianming Yang, Chunyuan Zhang, Liang Zhao:
The masala machine: accelerating thread-intensive and explicit memory management programs with dynamically reconfigurable FPGAs (abstract only). FPGA 2012: 265 - [c22]Changqing Xun, Mei Wen, Nan Wu, Chunyuan Zhang, Hayden Kwok-Hay So
Extending BORPH for shared memory reconfigurable computers. FPL 2012: 563-566 - [c21]Nan Wu, Mei Wen, Huayou Su, Ju Ren, Chunyuan Zhang:
A Parallel H.264 Encoder with CUDA: Mapping and Evaluation. ICPADS 2012: 276-283 - 2011
- [j3]Nan Wu, Qianming Yang, Mei Wen, Yi He, Ju Ren, Maolin Guan, Chunyuan Zhang:
Tiled Multi-Core Stream Architecture. Trans. High Perform. Embed. Archit. Compil. 4: 274-293 (2011) - [c20]Huayou Su, Nan Wu, Chunyuan Zhang, Mei Wen, Ju Ren:
A Multilevel Parallel Intra Coding for H.264/AVC Based on CUDA. ICIG 2011: 76-81 - [c19]Huayou Su, Chunyuan Zhang, Jun Chai, Mei Wen, Nan Wu, Ju Ren:
High-efficient software parallel CAVLC encoder based on programmable stream processor. ACM Multimedia 2011: 1333-1336 - [c18]Huayou Su, Chunyuan Zhang, Jun Chai, Mei Wen, Nan Wu, Ju Ren:
A high-efficient software parallel CAVCL encoder based on GPU. TSP 2011: 534-540 - 2010
- [c17]Qianming Yang, Nan Wu, Mei Wen, Yi He, Huayou Su, Chunyuan Zhang:
SAT: A Stream Architecture Template for Embedded Applications. CIT 2010: 1711-1718 - [c16]Yi He, Ju Ren, Mei Wen, Qianming Yang, Nan Wu, Chunyuan Zhang:
Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels. DSD 2010: 823-830 - [c15]Ju Ren, Mei Wen, Chunyuan Zhang, Huayou Su, Yi He, Nan Wu:
A Parallel Streaming Motion Estimation for Real-Time HD H.264 Encoding on Programmable Processors. FCST 2010: 154-160
2000 – 2009
- 2009
- [c14]Ju Ren, Yi He, Wei Wu, Mei Wen, Nan Wu, Chunyuan Zhang:
Software parallel CAVLC encoder based on stream processing. ESTIMedia 2009: 126-133 - [c13]Nan Wu, Mei Wen, Ju Ren, Yi He, Changqing Xun, Wei Wu, Chunyuan Zhang:
Cache streamization for high performance stream processor. HiPC 2009: 140-149 - [c12]Nan Wu, Mei Wen, Wei Wu, Ju Ren, Huayou Su, Changqing Xun, Chunyuan Zhang:
Streaming HD H.264 encoder on programmable processors. ACM Multimedia 2009: 371-380 - 2008
- [j2]Mei Wen, Nan Wu, Chunyuan Zhang, Qianming Yang, Ju Ren, Yi He, Wei Wu, Jun Chai, Maolin Guan, Changqing Xun:
On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator. IEEE Micro 28(4): 51-70 (2008) - [c11]Yi He, Ju Ren, Qianming Yang, Mei Wen, Nan Wu, Chunyuan Zhang:
FPGA-based Equivalent Simulation Technology (FEST) for clustered stream architecture. ACSAC 2008: 1-8 - [c10]Mei Wen, Nan Wu, Maolin Guan, Chunyuan Zhang:
Load scheduling: Reducing pressure on distributed register files for free. ASP-DAC 2008: 340-345 - 2007
- [c9]Nan Wu, Qianming Yang, Mei Wen, Yi He, Changqing Xun, Chunyuan Zhang:
A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision. Asia-Pacific Computer Systems Architecture Conference 2007: 256-267 - [c8]Mei Wen, Nan Wu, Chunyuan Zhang, Wei Wu, Qianming Yang, Changqing Xun:
FT64: Scientific Computing with Streams. HiPC 2007: 209-220 - 2006
- [c7]Mei Wen, Nan Wu, Changqing Xun, Wei Wu, Chunyuan Zhang:
Analysis and Performance Results of a fluid dynamics Application on MASA Stream Processor. ACIS-ICIS 2006: 350-354 - [c6]Mei Wen, Nan Wu, Changqing Xun, Wei Wu, Chunyuan Zhang:
Optimization and Evaluating of StreamYGX2 on MASA Stream Processor. Asia-Pacific Computer Systems Architecture Conference 2006: 531-537 - [c5]Nan Wu, Mei Wen, Ju Ren, Yi He, Chunyuan Zhang:
Register Allocation on Stream Processor with Local Register File. Asia-Pacific Computer Systems Architecture Conference 2006: 545-551 - 2005
- [j1]Mei Wen, Nan Wu, Haiyan Li, Chunyuan Zhang:
Multiple-Morphs Adaptive Stream Architecture. J. Comput. Sci. Technol. 20(5): 635-646 (2005) - [c4]Nan Wu, Mei Wen, Haiyan Li, Li Li, Chunyuan Zhang:
A Stream Architecture Supporting Multiple Stream Execution Models. Asia-Pacific Computer Systems Architecture Conference 2005: 143-156 - [c3]Haiyan Li, Mei Wen, Chunyuan Zhang, Nan Wu, Li Li, Changqing Xun:
Accelerated Motion Estimation of H.264 on Imagine Stream Processor. ICIAR 2005: 367-374 - 2004
- [c2]Mei Wen, Nan Wu, Haiyan Li, Chunyuan Zhang:
Multiple-Dimension Scalable Adaptive Stream Architecture. Asia-Pacific Computer Systems Architecture Conference 2004: 199-211 - [c1]Mei Wen, Chunyuan Zhang, Nan Wu, Haiyan Li, Li Li:
A Parallel Reed-Solomon Decoder on the Imagine Stream Processor. ISPA 2004: 28-33
Coauthor Index
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