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Guy Lemieux
Guy G. Lemieux – Guy G. F. Lemieux
Person information
- affiliation: University of British Columbia, Canada
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2020 – today
- 2023
- [j14]May Young
, Alan J. Hu
Cache Abstraction for Data Race Detection in Heterogeneous Systems with Non-coherent Accelerators. ACM Trans. Embed. Comput. Syst. 22(1): 6:1-6:25 (2023) - [j13]Zhonghua Zhou
MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing. ACM Trans. Design Autom. Electr. Syst. 28(5): 73:1-73:25 (2023) - 2022
- [c69]Mariko Tatsumi, Silviu-Ioan Filip, Caroline White, Olivier Sentieys, Guy Lemieux:
Mixing Low-Precision Formats in Multiply-Accumulate Units for DNN Training. FPT 2022: 1-9 - 2021
- [c68]May Young, Alan J. Hu
Cache abstraction for data race detection in heterogeneous systems with non-coherent accelerators. LCTES 2021: 151-162 - 2020
- [c67]Dingqing Yang
Procrustes: a Dataflow and Accelerator for Sparse Deep Neural Network Training. MICRO 2020: 711-724 - [i4]Dingqing Yang, Amin Ghasemazar, Xiaowei Ren, Maximilian Golub, Guy Lemieux, Mieszko Lis:
Procrustes: a Dataflow and Accelerator for Sparse Deep Neural Network Training. CoRR abs/2009.10976 (2020)
2010 – 2019
- 2019
- [c66]Hossein Omidian, Guy G. F. Lemieux:
Low-Level Loop Analysis and Pipelining of Applications Mapped to Xilinx FPGAs. FPL 2019: 391-396 - [c65]Hossein Omidian, Guy G. F. Lemieux:
Software-based Dynamic Overlays Require Fast, Fine-grained Partial Reconfiguration. HEART 2019: 13:1-13:6 - [c64]Maximilian Golub, Guy Lemieux, Mieszko Lis:
Full Deep Neural Network Training On A Pruned Weight Budget. SysML 2019 - [i3]Guy G. F. Lemieux, Joe Edwards, Joel Vandergriendt, Aaron Severance, Ryan De Iaco, Abdullah Raouf, Hussein Osman, Tom Watzka, Satwant Singh:
TinBiNN: Tiny Binarized Neural Network Overlay in about 5, 000 4-LUTs and 5mW. CoRR abs/1903.06630 (2019) - 2018
- [c63]Ameer M. S. Abdelhadi, Guy G. F. Lemieux, Lesley Shannon:
Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories. FPL 2018: 243-250 - [c62]Hossein Omidian, Nick Ivanov, Guy G. F. Lemieux:
An Accelerated OpenVX Overlay for Pure Software Programmers. FPT 2018: 290-293 - [i2]Maximilian Golub, Guy Lemieux, Mieszko Lis:
DropBack: Continuous Pruning During Training. CoRR abs/1806.06949 (2018) - 2017
- [c61]Joe Edwards, Guy G. F. Lemieux:
Real-time object detection in software with custom vector instructions and algorithm changes. ASAP 2017: 75-82 - [c60]Hossein Omidian, Guy G. F. Lemieux:
Exploring automated space/time tradeoffs for OpenVX compute graphs. FPT 2017: 152-159 - 2016
- [j12]Ameer M. S. Abdelhadi, Guy G. F. Lemieux:
Modular Switched Multiported SRAM-Based Memories. ACM Trans. Reconfigurable Technol. Syst. 9(3): 22:1-22:26 (2016) - [c59]Ameer M. S. Abdelhadi, Guy G. F. Lemieux:
A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs. FCCM 2016: 140-147 - [i1]Hossein Omidian, Guy G. F. Lemieux:
Automated Space/Time Scaling of Streaming Task Graph. CoRR abs/1606.03717 (2016) - 2015
- [j11]Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip Brisk
Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 1928-1941 (2015) - [c58]Michael Xi Yue, Dirk Koch, Guy G. F. Lemieux:
Rapid Overlay Builder for Xilinx FPGAs. FCCM 2015: 17-20 - [c57]Ameer M. S. Abdelhadi, Guy G. F. Lemieux:
Modular SRAM-Based Binary Content-Addressable Memories. FCCM 2015: 207-214 - [c56]Aaron Severance, Joe Edwards, Guy G. F. Lemieux:
Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors. FPGA 2015: 171-180 - [c55]Shao Lin S. T. Tang, Guy Lemieux:
Area Optimization of Arithmetic Units by Component Sharing for FPGAs (Abstract Only). FPGA 2015: 276 - 2014
- [c54]Ameer Abdelhadi, Guy G. F. Lemieux:
Modular multi-ported SRAM-based memories. FPGA 2014: 35-44 - [c53]Aaron Severance, Joe Edwards, Hossein Omidian, Guy Lemieux:
Soft vector processors with streaming pipelines. FPGA 2014: 117-126 - [c52]Ameer M. S. Abdelhadi, Guy G. F. Lemieux:
Deep and narrow binary content-addressable memories using FPGA-based BRAMs. FPT 2014: 318-321 - 2013
- [c51]Aaron Severance, Guy G. F. Lemieux:
Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor. CODES+ISSS 2013: 6:1-6:10 - [c50]Alexander Brant, Ameer Abdelhadi, Douglas H. H. Sim, Shao Lin Tang, Michael Xi Yue, Guy G. F. Lemieux:
Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using Razor. FCCM 2013: 37-44 - [c49]Dirk Koch, Christian Beckhoff, Guy G. F. Lemieux:
An efficient FPGA overlay for portable custom instruction set extensions. FPL 2013: 1-8 - [c48]Aaron Severance, Guy G. F. Lemieux:
TputCache: High-frequency, multi-way cache for high-throughput FPGA applications. FPL 2013: 1-6 - 2012
- [j10]David Grant, Graeme Smecher, Guy G. F. Lemieux, Rosemary Francis:
Rapid Synthesis and Simulation of Computational Circuits in an MPPA. J. Signal Process. Syst. 67(1): 47-63 (2012) - [c47]Alexander Brant, Guy G. F. Lemieux:
ZUMA: An Open FPGA Overlay Architecture. FCCM 2012: 93-96 - [c46]Aaron Severance, Guy Lemieux:
VENICE: A Compact Vector Processor for FPGA Applications. FCCM 2012: 245 - [c45]Zhiduo Liu, Aaron Severance, Satnam Singh, Guy G. F. Lemieux:
Accelerator compiler for the VENICE vector processor. FPGA 2012: 229-232 - [c44]Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA 2012: 255-264 - [c43]Chris C. Wang, Guy G. F. Lemieux:
Parallel FPGA placement based on individual LUT placement (abstract only). FPGA 2012: 269 - [c42]Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip Brisk
Routing algorithms for FPGAS with sparse intra-cluster routing crossbars. FPL 2012: 91-98 - [c41]Alexander Brant, Ameer Abdelhadi, Aaron Severance, Guy G. F. Lemieux:
Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew. FPT 2012: 235-238 - [c40]Aaron Severance, Guy Lemieux:
VENICE: A compact vector processor for FPGA applications. FPT 2012: 261-268 - 2011
- [j9]Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton:
Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs). IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2195-2208 (2011) - [c39]Jonathan Rose, Guy G. Lemieux:
The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop. FPGA 2011: 1-2 - [c38]Christopher Han-Yu Chou, Aaron Severance, Alex D. Brant, Zhiduo Liu, Saurabh Sant, Guy G. Lemieux:
VEGAS: soft vector processor with scratchpad memory. FPGA 2011: 15-24 - [c37]David Grant, Chris C. Wang, Guy G. Lemieux:
A CAD framework for Malibu: an FPGA with time-multiplexed coarse-grained elements. FPGA 2011: 123-132 - [c36]Chris C. Wang, Guy G. Lemieux:
Scalable and deterministic timing-driven parallel placement for FPGAs. FPGA 2011: 153-162 - [c35]Aaron Severance, Guy Lemieux:
VENICE: A compact vector processor for FPGA applications. Hot Chips Symposium 2011: 1-5 - [c34]Ameer Abdelhadi, Guy G. F. Lemieux:
Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations. ReConFig 2011: 20-26 - [c33]Jeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton:
Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition. ReConFig 2011: 41-48 - 2010
- [j8]Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, William G. Dunford, Patrick R. Palmer
A 4 GHz Non-Resonant Clock Driver With Inductor-Assisted Energy Return to Power Grid. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(8): 2099-2108 (2010) - [c32]Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton:
The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). FPGA 2010: 263-272
2000 – 2009
- 2009
- [j7]Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux:
Vector Processing as a Soft Processor Accelerator. ACM Trans. Reconfigurable Technol. Syst. 2(2): 12:1-12:34 (2009) - [c31]Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet:
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. FPGA 2009: 43-52 - [c30]Johnny Tsung Lin Ho, Guy G. Lemieux:
PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions. FPGA 2009: 257-260 - [c29]David Leong, Guy G. Lemieux:
Replace: An incremental placement algorithm for field programmable gate arrays. FPL 2009: 154-161 - [c28]Xiao Dong, Guy G. F. Lemieux:
PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess. FPT 2009: 88-95 - [c27]David Grant, Graeme Smecher, Guy Lemieux, Rosemary Francis:
Rapid synthesis and simulation of computational circuits in an MPPA. FPT 2009: 151-158 - [c26]Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet:
Estimating reliability and throughput of source-synchronous wave-pipelined interconnect. NOCS 2009: 234-243 - 2008
- [j6]David Grant, Guy G. Lemieux:
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing. ACM Trans. Reconfigurable Technol. Syst. 1(3): 16:1-16:24 (2008) - [j5]Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton:
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. IEEE Trans. Very Large Scale Integr. Syst. 16(11): 1521-1534 (2008) - [j4]Edmund Lee, Guy Lemieux, Shahriar Mirabbasi:
Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays. J. Signal Process. Syst. 51(1): 57-76 (2008) - [c25]Guy G. Lemieux, Tarek A. El-Ghazawi:
Designing with extreme parallelism. FPGA 2008: 1-2 - [c24]Tarek A. El-Ghazawi, Guy G. Lemieux:
Extreme parallel architectures for the masses. FPGA 2008: 127-128 - [c23]Jason Yu, Guy G. Lemieux, Christopher Eagleston:
Vector processing as a soft-core CPU accelerator. FPGA 2008: 222-232 - [c22]Johnny Tsung Lin Ho, Guy G. F. Lemieux:
PERG: A scalable FPGA-based pattern-matching engine with consolidated Bloomier filters. FPT 2008: 73-80 - [c21]Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, William G. Dunford, Patrick R. Palmer
Energy Recovery from High-Frequency Clocks Using DC-DC Converters. ISVLSI 2008: 162-167 - 2007
- [j3]Paul Teehan, Mark R. Greenstreet, Guy G. Lemieux:
A Survey and Taxonomy of GALS Design Styles. IEEE Des. Test Comput. 24(5): 418-428 (2007) - [c20]Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton:
GlitchLess: an active glitch minimization technique for FPGAs. FPGA 2007: 156-165 - [c19]Jason Yu, Guy Lemieux:
A Case for Soft Vector Processors in FPGAs. FPT 2007: 341-344 - [c18]Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, Patrick R. Palmer
A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter. ISSCC 2007: 532-620 - [c17]David Yeager, Darius Chiu, Guy G. Lemieux:
Congestion estimation and localization in FPGAS: a visual tool for interconnect prediction. SLIP 2007: 33-40 - 2006
- [j2]Resve A. Saleh, Steven J. E. Wilton, Shahriar Mirabbasi, Alan J. Hu, Mark R. Greenstreet, Guy Lemieux, Partha Pratim Pande, Cristian Grecu, André Ivanov:
System-on-Chip: Reuse and Integration. Proc. IEEE 94(6): 1050-1069 (2006) - [c16]David Grant, Scott Chin, Guy G. Lemieux:
Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools. FPL 2006: 1-4 - [c15]Edmund Lee, Guy Lemieux, Shahriar Mirabbasi:
Interconnect driver design for long wires in field-programmable gate arrays. FPT 2006: 89-96 - [c14]David Grant, Guy Lemieux:
Perturber: semi-synthetic circuit generation using ancestor control for testing incremental place and route. FPT 2006: 189-196 - [c13]Marvin Tom, David Leong, Guy G. Lemieux:
Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. ICCAD 2006: 680-687 - 2005
- [c12]Victor O. Aken'Ova, Guy Lemieux, Resve A. Saleh:
An improved "soft" eFPGA design and implementation strategy. CICC 2005: 179-182 - [c11]Marvin Tom, Guy G. Lemieux:
Logic block clustering of large designs for channel-width constrained FPGAs. DAC 2005: 726-731 - [c10]Anthony J. Yu, Guy G. Lemieux:
Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement. FPL 2005: 255-262 - [c9]Anthony J. Yu, Guy G. Lemieux:
FPGA Defect Tolerance: Impact of Granularity. FPT 2005: 189-196 - 2004
- [b1]Guy Lemieux, David A. Lewis:
Design of interconnection networks for programmable logic. Kluwer 2004, ISBN 978-1-4020-7700-5, pp. I-XX, 1-206 - [c8]Guy Lemieux, Edmund Lee, Marvin Tom, Anthony J. Yu:
Directional and single-driver wires in FPGA interconnect. FPT 2004: 41-48 - 2002
- [c7]Guy G. Lemieux, David M. Lewis:
Circuit design of routing switches. FPGA 2002: 19-28 - [c6]Guy G. Lemieux, David M. Lewis:
Analytical Framework for Switch Block Design. FPL 2002: 122-131 - 2001
- [c5]Guy G. Lemieux, David M. Lewis:
Using sparse crossbars within LUT. FPGA 2001: 59-68 - 2000
- [c4]Guy G. Lemieux, Paul Leventis, David M. Lewis:
Generating highly-routable sparse crossbars for PLDs. FPGA 2000: 155-164 - [c3]R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic:
The NUMAchine Multiprocessor. ICPP 2000: 487-496
1990 – 1999
- 1998
- [c2]A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic:
Design and Implementation of the NUMAchine Multiprocessor. DAC 1998: 66-69 - 1997
- [c1]Guy G. Lemieux, Stephen Dean Brown, Daniel Vranesic:
On two-step routing for FPGAS. ISPD 1997: 60-66 - 1996
- [j1]Stephen Dean Brown, Muhammad M. Khellah
Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays. VLSI Design 4(4): 275-291 (1996)
Coauthor Index
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