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Kiyoshi Oguri
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2010 – 2019
- 2019
- [c57]Naofumi Yoshinaga, Ryo Kamasaka, Yuichiro Shibata, Kiyoshi Oguri:
Pipelined FPGA Implementation of a Wave-Front-Fetch Graph Cut System. CISIS 2019: 430-441 - 2018
- [j18]Taito Manabe, Yuichiro Shibata, Kiyoshi Oguri:
FPGA Implementation of a Real-Time Super-Resolution System Using Flips and an RNS-Based CNN. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2280-2289 (2018) - [c56]Kazuya Uetsuhara, Hiroki Nagayama, Yuichiro Shibata, Kiyoshi Oguri:
Discussion on High Level Synthesis FPGA Design of Camera Calibration. CISIS 2018: 538-549 - [c55]Ryo Kamasaka, Yuichiro Shibata, Kiyoshi Oguri:
An FPGA-oriented Graph Cut Algorithm for Accelerating Stereo Vision. ReConFig 2018: 1-6 - [i1]Kiyoshi Oguri, Yuichiro Shibata:
A new stereo formulation not using pixel and disparity models. CoRR abs/1803.01516 (2018) - 2017
- [j17]Theint Theint Thu, Jimpei Hamamura, Rie Soejima, Yuichiro Shibata, Kiyoshi Oguri:
Comparative Evaluation of FPGA Implementation Alternatives for Real-Time Robust Ellipse Estimation based on RANSAC Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1409-1417 (2017) - [j16]Theint Theint Thu, Yoshiki Hayashida, Akane Tahara, Yuichiro Shibata, Kiyoshi Oguri:
Deep-pipelined FPGA Implementation of Real-time Object Tracking using a Particle Filter. Int. J. Netw. Comput. 7(2): 372-386 (2017) - [c54]Akane Tahara, Yoshiki Hayashida, Theint Theint Thu, Yuichiro Shibata, Kiyoshi Oguri:
Power Performance Analysis of FPGA-Based Particle Filtering for Realtime Object Tracking. CISIS 2017: 451-462 - [c53]Rie Soejima, Yuichiro Shibata, Kiyoshi Oguri:
HLS-Based FPGA Acceleration of Building-Cube Stencil Computation. CISIS 2017: 463-474 - [c52]Taito Manabe, Yuichiro Shibata, Kiyoshi Oguri:
FPGA implementation of a real-time super-resolution system with a CNN based on a residue number system. FPT 2017: 299-300 - [c51]Ryo Kamasaka, Yuichiro Shibata, Kiyoshi Oguri:
FPGA Implementation of A Graph Cut Algorithm For Stereo Vision. HEART 2017: 14:1-14:6 - 2016
- [c50]Masahito Oishi, Yoshiki Hayashida, Ryo Fujita, Yuichiro Shibata, Kiyoshi Oguri:
A Comparison of Machine Learning Classifiers for FPGA Implementation of HOG-Based Human Detection. ARC 2016: 91-104 - [c49]Taito Manabe, Yuichiro Shibata, Kiyoshi Oguri:
FPGA implementation of a real-time super-resolution system using a convolutional neural network. FPT 2016: 249-252 - [c48]Akane Tahara, Yoshiki Hayashida, Theint Theint Thu, Yuichiro Shibata, Kiyoshi Oguri:
FPGA-based Real-Time Object Tracking Using a Particle Filter with Stream Architecture. CANDAR 2016: 422-428 - 2015
- [j15]Keisuke Dohi, Koji Okina, Rie Soejima, Yuichiro Shibata, Kiyoshi Oguri:
Performance Modeling of Stencil Computing on a Stream-Based FPGA Accelerator for Efficient Design Space Exploration. IEICE Trans. Inf. Syst. 98-D(2): 298-308 (2015) - [j14]Koji Okina, Rie Soejima, Kota Fukumoto, Yuichiro Shibata, Kiyoshi Oguri:
Power Performance Profiling of 3-D Stencil Computation on an FPGA Accelerator for Efficient Pipeline Optimization. SIGARCH Comput. Archit. News 43(4): 9-14 (2015) - [c47]Aiko Iwasaki, Yuichiro Shibata, Kiyoshi Oguri, Ryuichi Harasawa:
An energy-efficient FPGA-based soft-core processor with a configurable word size ECC arithmetic accelerator. COOL Chips 2015: 1-3 - [c46]Makoto Fujimura, Shuhei Sato, Toshio Higashi, Kiyoshi Oguri:
Study of mirror box therapy support system by leap motion. ICCE-TW 2015: 430-431 - 2014
- [j13]Rie Soejima, Koji Okina, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri:
A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis. SIGARCH Comput. Archit. News 42(4): 69-74 (2014) - [c45]Kaoru Hamasaki, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri:
FPGA Implementation of a Video Based Abnormal Action Detection System with Real-Time Cubic Higher Order Local Auto-Correlation Analysis. ARC 2014: 191-196 - [c44]Aiko Iwasaki, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Ryuichi Harasawa:
A soft-core processor for finite field arithmetic with a variable word size accelerator. FPL 2014: 1-4 - 2013
- [j12]Keisuke Dohi, Kazuhiro Negi, Yuichiro Shibata, Kiyoshi Oguri:
FPGA Implementation of Human Detection by HOG Features with AdaBoost. IEICE Trans. Inf. Syst. 96-D(8): 1676-1684 (2013) - [c43]Kota Aoki, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Takafumi Fujimoto:
A Fast Runtime Visualization of a GPU-Based 3D-FDTD Electromagnetic Simulation. CANDAR 2013: 30-37 - [c42]Keisuke Dohi, Kota Fukumoto, Yuichiro Shibata, Kiyoshi Oguri:
Performance modeling and optimization of 3-D stencil computation on a stream-based FPGA accelerator. ReConFig 2013: 1-6 - 2012
- [j11]Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Takafumi Fujimoto:
Implementation of a GPU-Oriented Absorbing Boundary Condition for 3D-FDTD Electromagnetic Simulation. IEICE Trans. Inf. Syst. 95-D(12): 2787-2795 (2012) - [j10]Takeshi Kakimoto, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri:
Performance comparison of GPU programming frameworks with the striped Smith-Waterman algorithm. SIGARCH Comput. Archit. News 40(5): 70-75 (2012) - [c41]Keisuke Dohi, Yuma Hatanaka, Kazuhiro Negi, Yuichiro Shibata, Kiyoshi Oguri:
Deep-pipelined FPGA implementation of ellipse estimation for eye tracking. FPL 2012: 458-463 - 2011
- [j9]Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Takafumi Fujimoto:
GPU implementation and optimization of electromagnetic simulation using the FDTD method for antenna designing. SIGARCH Comput. Archit. News 39(4): 26-31 (2011) - [j8]Kohei Matsunobu, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri:
A discussion on calculating eigenvalues of real symmetric tridiagonal matrices on a GPU. SIGARCH Comput. Archit. News 39(4): 100-101 (2011) - [c40]Keisuke Dohi, Yuji Yorita, Yuichiro Shibata, Kiyoshi Oguri:
Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation. FPL 2011: 478-481 - [c39]Kazuhiro Negi, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri:
Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm. FPT 2011: 1-8 - [c38]Tomonari Masada, Atsuhiro Takasu, Yuichiro Shibata, Kiyoshi Oguri:
Semi-supervised Bibliographic Element Segmentation with Latent Permutations. ICADL 2011: 60-69 - [c37]Tomonari Masada, Yuichiro Shibata, Kiyoshi Oguri:
Documents as a Bag of Maximal Substrings - An Unsupervised Feature Extraction for Document Clustering. ICEIS (1) 2011: 5-13 - [c36]Tomonari Masada, Atsuhiro Takasu, Yuichiro Shibata, Kiyoshi Oguri:
Clustering Documents with Maximal Substrings. ICEIS 2011: 19-34 - [c35]Tomonari Masada, Atsuhiro Takasu, Yuichiro Shibata, Kiyoshi Oguri:
Steering Time-Dependent Estimation of Posteriors with Hyperparameter Indexing in Bayesian Topic Models. PAKDD (1) 2011: 435-447 - 2010
- [j7]Hideki Yamada, Yui Ogawa, Tomonori Ooya, Tomoya Ishimori, Yasunori Osana
, Masato Yoshimi, Yuri Nishikawa
Automatic Pipeline Construction Focused on Similarity of Rate Law Functions for an FPGA-based Biochemical Simulator. IPSJ Trans. Syst. LSI Des. Methodol. 3: 244-256 (2010) - [j6]Keisuke Dohi, Yuichiro Shibata, Tsuyoshi Hamada, Tomonari Masada, Kiyoshi Oguri, Duncan A. Buell:
Implementation of a programming environment with a multithread model for reconfigurable systems. SIGARCH Comput. Archit. News 38(4): 40-45 (2010) - [c34]Tomonari Masada, Yuichiro Shibata, Kiyoshi Oguri:
Infinite latent process decomposition. BIBM Workshops 2010: 810-811 - [c33]Yui Ogawa, Tomonori Ooya, Yasunori Osana
A datapath classification method for FPGA-based scientific application accelerator systems. FPT 2010: 441-444 - [c32]Tomonari Masada, Daiji Fukagawa, Atsuhiro Takasu, Yuichiro Shibata, Kiyoshi Oguri:
Modeling Topical Trends over Continuous Time with Priors. ISNN (2) 2010: 302-311 - [c31]Tomonari Masada, Yuichiro Shibata, Kiyoshi Oguri:
Unsupervised Segmentation of Bibliographic Elements with Latent Permutations. WISE Workshops 2010: 254-267
2000 – 2009
- 2009
- [j5]Tsuyoshi Hamada, Keigo Nitadori, Khaled Benkrid, Yousuke Ohno, Gentaro Morimoto, Tomonari Masada, Yuichiro Shibata, Kiyoshi Oguri, Makoto Taiji:
A novel multiple-walk parallel algorithm for the Barnes-Hut treecode on GPUs - towards cost effective, high performance N-body simulation. Comput. Sci. Res. Dev. 24(1-2): 21-31 (2009) - [c30]Tomonari Masada, Tsuyoshi Hamada, Yuichiro Shibata, Kiyoshi Oguri:
Bayesian Multi-topic Microarray Analysis with Hyperparameter Reestimation. ADMA 2009: 253-264 - [c29]Kentaro Matsuo, Tsuyoshi Hamada, Masayuki Miyoshi, Yuichiro Shibata, Kiyoshi Oguri:
Accelerating Phase Correlation Functions Using GPU and FPGA. AHS 2009: 433-438 - [c28]Tomoya Ishimori, Hideki Yamada, Yuichiro Shibata, Yasunori Osana
Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator. ARC 2009: 368-373 - [c27]Tomonari Masada, Daiji Fukagawa, Atsuhiro Takasu, Tsuyoshi Hamada, Yuichiro Shibata, Kiyoshi Oguri:
Dynamic hyperparameter optimization for bayesian topical trend analysis. CIKM 2009: 1831-1834 - [c26]Tomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata, Yasunori Osana
Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator. FPL 2009: 679-682 - [c25]Tomonari Masada, Tsuyoshi Hamada, Yuichiro Shibata, Kiyoshi Oguri:
Accelerating Collapsed Variational Bayesian Inference for Latent Dirichlet Allocation with Nvidia CUDA Compatible Devices. IEA/AIE 2009: 491-500 - [c24]Hideki Yamada, Yasunori Osana
A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA. ReConFig 2009: 125-130 - [c23]Tomonari Masada, Atsuhiro Takasu, Tsuyoshi Hamada, Yuichiro Shibata, Kiyoshi Oguri:
Bag of Timestamps: A Simple and Efficient Bayesian Chronological Mining. APWeb/WAIM 2009: 556-561 - 2008
- [c22]Hidenori Matsubayashi, Shinsuke Nino, Toru Aramaki, Yuichiro Shibata, Kiyoshi Oguri:
Retrieving 3-d information with FPGA-based stream processing. FPGA 2008: 261 - [c21]Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. Buell
An optimization method of DMA transfer for a general purpose reconfigurable machine. FPL 2008: 647-650 - 2007
- [j4]Miwa Miyata, Yuichiro Shibata, Kiyoshi Oguri:
An optimization method focusing on fixed-point arithmetic in applications for dynamically reconfigurable processor. Syst. Comput. Jpn. 38(14): 20-28 (2007) - [c20]Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. Buell
Implementation of a barotropic operator for ocean model simulation using a reconfigurable machine. FPL 2007: 589-592 - [c19]Hideki Yamada, Naoki Iwanaga
A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator. FPL 2007: 808-811 - [c18]Shinsuke Nino, Takayuki Mori, YoungHun Ko, Yuichiro Shibata, Kiyoshi Oguri:
FPGA Implementation of a Statically Reconfigurable Java Environment for Embedded Systems. FPT 2007: 317-320 - 2006
- [c17]Miwa Miyata, Hideyuki Tsuchiya, Yuichiro Shibata, Kiyoshi Oguri:
An Implementation Technique of Multi-Cycled Arithmetic Functions For a Dynamically Reconfigurable Processor. FPL 2006: 1-4 - 2005
- [c16]Taichi Nagamoto, Satoshi Yano, Mitsuru Uchida, Yuichiro Shibata, Kiyoshi Oguri:
New Area Management Method Based on "Pressure" for Plastic Cell Architecture. EUC 2005: 418-427 - [c15]Shinya Kyusaka, Hayato Higuchi, Taichi Nagamoto, Yuichiro Shibata, Kiyoshi Oguri:
Evaluation of Space Allocation Circuits. EUC 2005: 428-437 - [c14]Naoki Iwanaga, Yuichiro Shibata, Masato Yoshimi, Yasunori Osana
Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA. FPL 2005: 666-669 - 2004
- [c13]Takehiro Ito, Yuichiro Shibata, Kiyoshi Oguri:
Implementation of the Extended Euclidean Algorithm for the Tate Pairing on FPGA. FPL 2004: 911-916 - 2003
- [c12]Kiyoshi Oguri, Yuichiro Shibata, Akira Nagoya:
Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA. Asia-Pacific Computer Systems Architecture Conference 2003: 54-68 - 2002
- [j3]Minoru Inamori, Hiroshi Nakada, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri:
A Method of Mapping Finite State Machine into PCA Plastic Parts. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 804-810 (2002) - 2001
- [c11]Ryusuke Konishi, Hideyuki Ito, Hiroshi Nakada, Akira Nagoya, Norbert Imlig, Tsunemichi Shiozawa, Minoru Inamori, Kouichi Nagami, Kiyoshi Oguri:
PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI. ASYNC 2001: 54- - [c10]Hiroshi Nakada, Hideyuki Ito, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri, Tsunemichi Shiozawa, Norbert Imlig:
Self-reorganising systems on VLSI circuits. ISCAS (4) 2001: 310-313 - 2000
- [c9]Norbert Imlig, Ryusuke Konishi, Tsunemichi Shiozawa, Kiyoshi Oguri, Kouichi Nagami, Hideyuki Ito, Minoru Inamori, Hiroshi Nakada:
Communicating logic: an alternative embedded stream processing paradigm. ASP-DAC 2000: 317-322 - [c8]Tsunemichi Shiozawa, Norbert Imlig, Kouichi Nagami, Kiyoshi Oguri, Akira Nagoya, Hiroshi Nakada:
An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture. FPL 2000: 805-809
1990 – 1999
- 1999
- [c7]Hiroshi Nakada, Kiyoshi Oguri, Norbert Imlig, Minoru Inamori, Ryusuke Konishi, Hideyuki Ito, Kouichi Nagami, Tsunemichi Shiozawa:
Plastic Cell Architecture: A Dynamically Reconfigurable Hardware-Based Computer. IPPS/SPDP Workshops 1999: 679-687 - 1998
- [j2]Hiroyuki Yamashita, Toshihiko Suguri, Shingo Kinoshita, Yasushi Okada, Kiyoshi Oguri:
Message routing latency-minimizing method in an ASIC design for distributed cooperative communication protocol processing. Syst. Comput. Jpn. 29(3): 39-58 (1998) - [c6]Kouichi Nagami, Kiyoshi Oguri, Tsunemichi Shiozawa, Hideyuki Ito, Ryusuke Konishi:
Plastic Cell Architecture: Towards Reconfigurable Computing for General-Purpose. FCCM 1998: 68-77 - [c5]Tsunemichi Shiozawa, Kiyoshi Oguri, Kouichi Nagami, Hideyuki Ito, Ryusuke Konishi, Norbert Imlig:
A Hardware Implementation of Constraint Satisfaction Problem Based on New Reconfigurable LSI Architecture. FPL 1998: 426-430 - [c4]Kiyoshi Oguri, Norbert Imlig, Hideyuki Ito, Kouichi Nagami, Ryusuke Konishi, Tsunemichi Shiozawa:
General-Purpose Computer Architecture Based on Fully Programmable Logic. ICES 1998: 323-334 - [c3]Hideyuki Ito, Kiyoshi Oguri, Kouichi Nagami, Ryusuke Konishi, Tsunemichi Shiozawa:
The Plastic Cell Architecture for Dynamic Reconfigurable Computing. International Workshop on Rapid System Prototyping 1998: 39-44 - 1995
- [j1]Mitsuteru Yukishita, Kiyoshi Oguri, Tsukasa Kawaoka:
Test Synthesis from Behavioral Description Based on Data Transfer Analysis. IEICE Trans. Inf. Syst. 78-D(3): 248-251 (1995) - 1990
- [c2]Akira Nagoya, Yukihiro Nakamura, Kiyoshi Oguri, Ryo Nomura:
Multi-Level Optimization for Large Scale ASICS. ICCAD 1990: 564-567 - [c1]Hiroshi Nakada, Naoya Sakurai, Yukiharu Kanayama, Naohisa Ohta, Kiyoshi Oguri:
Vector processor design for parallel DSP systems using hierarchical behavioral description based synthesizer. ICCD 1990: 86-89
Coauthor Index
[c57] [j18] [c56] [c55] [i1] [j17] [j16] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [j15] [j14] [c47] [j13] [c45] [c44] [j12] [c43] [c42] [j11] [j10] [c41] [j9] [j8] [c40] [c39] [c38] [c37] [c36] [c35] [j7] [j6] [c34] [c33] [c32] [c31] [j5] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [j4] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12]
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