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Giorgos Dimitrakopoulos
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2020 – today
- 2024
- [j34]Dionysios Filippas, Christodoulos Peltekis, Vasileios Titopoulos, Ioannis Kansizoglou, Georgios Ch. Sirakoulis, Antonios Gasteratos, Giorgos Dimitrakopoulos:
A High-Level Synthesis Library for Synthesizing Efficient and Functional-Safe CNN Dataflow Accelerators. IEEE Access 12: 57194-57208 (2024) - [j33]Christodoulos Peltekis, Vasileios Titopoulos, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity. IEEE Comput. Archit. Lett. 23(1): 17-20 (2024) - [c53]Christodoulos Peltekis, Kosmas Alexandridis, Giorgos Dimitrakopoulos:
Reusing Softmax Hardware Unit for GELU Computation in Transformers. AICAS 2024: 159-163 - [c52]Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos:
Error Checking for Sparse Systolic Tensor Arrays. AICAS 2024: 552-556 - [c51]Vasileios Titopoulos, K. Alexandridis, Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications. DATE 2024: 1-6 - [i10]Christodoulos Peltekis, Vasileios Titopoulos, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity. CoRR abs/2401.08179 (2024) - [i9]Christodoulos Peltekis, Kosmas Alexandridis, Giorgos Dimitrakopoulos:
Reusing Softmax Hardware Unit for GELU Computation in Transformers. CoRR abs/2402.10118 (2024) - [i8]Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos:
Error Checking for Sparse Systolic Tensor Arrays. CoRR abs/2402.10850 (2024) - 2023
- [j32]Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos:
Exploiting data encoding and reordering for low-power streaming in systolic arrays. Microprocess. Microsystems 102: 104938 (2023) - [j31]Dimitrios Mangiras, David G. Chinnery, Giorgos Dimitrakopoulos:
Task-Based Parallel Programming for Gate Sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1309-1322 (2023) - [j30]Dionysios Filippas, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
Streaming Dilated Convolution Engine. IEEE Trans. Very Large Scale Integr. Syst. 31(3): 401-405 (2023) - [j29]Apostolos Stefanidis, Ioanna Zoumpoulidou, Dionysios Filippas, Giorgos Dimitrakopoulos, Georgios Ch. Sirakoulis:
Synthesis of Approximate Parallel-Prefix Adders. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1686-1699 (2023) - [c50]Dionysios Filippas, Christodoulos Peltekis, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos:
Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines. AICAS 2023: 1-5 - [c49]Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos, Dionisios N. Pnevmatikatos:
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining. DATE 2023: 1-6 - [c48]Giorgos Dimitrakopoulos, E. Kallitsounakis, Z. Takakis, A. Stefanidis, Chrysostomos Nicopoulos:
Multi-Armed Bandits for Autonomous Test Application in RISC-V Processor Verification. MOCAST 2023: 1-5 - [c47]Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos:
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating. MOCAST 2023: 1-4 - [i7]Dionysios Filippas, Christodoulos Peltekis, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos:
Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines. CoRR abs/2304.01668 (2023) - [i6]Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos:
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating. CoRR abs/2304.12691 (2023) - [i5]Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos A. Nicopoulos:
The Case for Asymmetric Systolic Array Floorplanning. CoRR abs/2309.02969 (2023) - [i4]Vasileios Titopoulos, K. Alexandridis, Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications. CoRR abs/2311.07241 (2023) - 2022
- [j28]Dionysios Filippas, Nikolaos Margomenos, Nikolaos Mitianoudis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
Low-Cost Online Convolution Checksum Checker. IEEE Trans. Very Large Scale Integr. Syst. 30(2): 201-212 (2022) - [c46]Christodoulos Peltekis, Dionysios Filippas, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
FusedGCN: A Systolic Three-Matrix Multiplication Architecture for Graph Convolutional Networks. ASAP 2022: 93-97 - [c45]Dionysios Filippas, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
LeapConv: An Energy-Efficient Streaming Convolution Engine with Reconfigurable Stride. ISVLSI 2022: 200-205 - [c44]Yiannakis Sazeides, Alex Gerber, Ron Gabor, Arkady Bramnik, George Papadimitriou, Dimitris Gizopoulos, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Karyofyllis Patsidis:
IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming. MICRO 2022: 799-814 - [c43]Giorgos Dimitrakopoulos, Anastasios Psarras, Chrysostomos Nicopoulos:
Virtual-Channel Flow Control Across Mesochronous Clock Domains. MOCAST 2022: 1-4 - [i3]Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos, Dionisios N. Pnevmatikatos:
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining. CoRR abs/2211.12600 (2022) - 2021
- [j27]Dimitris Konstantinou, Chrysostomos Nicopoulos, Junghee Lee, Giorgos Dimitrakopoulos:
Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching. Integr. 77: 104-112 (2021) - [j26]Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, David G. Chinnery, Giorgos Dimitrakopoulos:
Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1672-1686 (2021) - [j25]Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras:
Sum Propagate Adders. IEEE Trans. Emerg. Top. Comput. 9(3): 1479-1488 (2021) - [c42]Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras:
Sum Propagate Adders. ARITH 2021: 110 - [c41]Dimitrios Mangiras, Giorgos Dimitrakopoulos:
Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment. MOCAST 2021: 1-5 - 2020
- [j24]Dimitrios Mangiras, Apostolos Stefanidis, Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2835-2848 (2020) - [j23]Dimitrios Konstantinou, Anastasios Psarras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
The Mesochronous Dual-Clock FIFO Buffer. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 302-306 (2020) - [c40]Yiannakis Sazeides, Arkady Bramnik, Ron Gabor, Chrysostomos Nicopoulos, Ramon Canal, Dimitris Konstantinou, Giorgos Dimitrakopoulos:
2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD). DFT 2020: 1-4 - [c39]Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, Rafailia-Eleni Karamani, Vasileios G. Ntinas, Giorgos Dimitrakopoulos, Sorin Cotofana, Georgios Ch. Sirakoulis:
Memristive Oscillatory Circuits for Resolution of NP-Complete Logic Puzzles: Sudoku Case. ISCAS 2020: 1-5 - [c38]Dimitrios Konstantinou, Chrysostomos Nicopoulos, Junghee Lee, Georgios Ch. Sirakoulis, Giorgos Dimitrakopoulos:
SmartFork: Partitioned Multicast Allocation and Switching in Network-on-Chip Routers. ISCAS 2020: 1-5 - [c37]Karyofyllis Patsidis, Chrysostomos Nicopoulos, Georgios Ch. Sirakoulis, Giorgos Dimitrakopoulos:
RISC-V2: A Scalable RISC-V Vector Processor. ISCAS 2020: 1-5 - [c36]Dimitrios Mangiras, Pavlos M. Mattheakis, Pierre-Olivier Ribet, Giorgos Dimitrakopoulos:
Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV. ISPD 2020: 25-32 - [c35]Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, David G. Chinnery, Giorgos Dimitrakopoulos:
Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation. ISPD 2020: 87-94 - [c34]Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, Vasileios G. Ntinas, Orestis Liolis, Giorgos Dimitrakopoulos, Mustafa Altun, Andrew Adamatzky, Mircea R. Stan, Georgios Ch. Sirakoulis:
Memristive Learning Cellular Automata: Theory and Applications. MOCAST 2020: 1-5 - [i2]Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, Rafailia-Eleni Karamani, Vasileios G. Ntinas, Giorgos Dimitrakopoulos, Sorin Cotofana, Georgios Ch. Sirakoulis:
Memristive oscillatory circuits for resolution of NP-complete logic puzzles: Sudoku case. CoRR abs/2002.06339 (2020) - [i1]Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, Vasileios G. Ntinas, Orestis Liolis, Giorgos Dimitrakopoulos, Mustafa Altun, Andrew Adamatzky, Mircea R. Stan, Georgios Ch. Sirakoulis:
Memristive Learning Cellular Automata: Theory and Applications. CoRR abs/2003.06983 (2020)
2010 – 2019
- 2019
- [j22]Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
Automatic Generation of Peak-Power Traffic for Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1): 96-108 (2019) - [j21]Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery:
Timing-Driven and Placement-Aware Multibit Register Composition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(8): 1501-1514 (2019) - [c33]Ron Gabor, Yiannakis Sazeides, Arkady Bramnik, Alexandros Andreou, Chrysostomos Nicopoulos, Karyofyllis Patsidis, Dimitris Konstantinou, Giorgos Dimitrakopoulos:
Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core. DATE 2019: 812-817 - [c32]Zacharias Takakis, Dimitrios Mangiras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional Coverage. IVSW 2019: 61-66 - [c31]Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
Multi-Armed Bandits for Autonomous Timing-driven Design Optimization. PATMOS 2019: 17-22 - 2018
- [j20]Karyofyllis Patsidis, Dimitris Konstantinou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension. Microprocess. Microsystems 61: 1-10 (2018) - [c30]Dimitris Konstantinou, Anastasios Psarras, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos:
Low-power dual-edge-triggered synchronous latency-insensitive systems. MOCAST 2018: 1-4 - 2017
- [j19]Emmanuel Karampasis, Nick P. Papanikolaou, Dionisis Voglitsis, Michael Loupis, Anastasios Psarras, Alexandros Boubaris, Dimitris Baros, Giorgos Dimitrakopoulos:
Active Thermoelectric Cooling Solutions for Airspace Applications: the THERMICOOL Project. IEEE Access 5: 2288-2299 (2017) - [j18]Anastasios Psarras, Michalis Paschou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
A Dual-Clock Multiple-Queue Shared Buffer. IEEE Trans. Computers 66(10): 1809-1815 (2017) - [j17]Anastasios Psarras, Savvas Moisidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
Networks-on-Chip With Double-Data-Rate Links. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(12): 3103-3114 (2017) - [c29]Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery:
Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation. DAC 2017: 56:1-56:6 - [c28]Monobrata Debnath, Dimitris Konstantinou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Wei-Ming Lin, Junghee Lee:
Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling. AISTECS@HiPEAC 2017: 8-11 - 2016
- [j16]Kypros Chrysanthou, Panayiotis Englezakis, Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos, Yiannakis Sazeides, Giorgos Dimitrakopoulos:
An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures. ACM Trans. Archit. Code Optim. 13(2): 22:1-22:26 (2016) - [j15]Anastasios Psarras, Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing. IEEE Trans. Computers 65(10): 3136-3147 (2016) - [j14]Anastasios Psarras, Junghee Lee, Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(5): 844-857 (2016) - [c27]Michalis Paschou, Anastasios Psarras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
CrossOver: Clock domain crossing under virtual-channel flow control. DATE 2016: 1183-1188 - [c26]Anastasios Psarras, Junghee Lee, Pavlos M. Mattheakis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors. ACM Great Lakes Symposium on VLSI 2016: 335-340 - [c25]Anastasios Psarras, Savvas Moisidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
RapidLink: A network-on-chip architecture with double-data-rate links. ICECS 2016: 93-96 - [c24]Ioannis Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
Powermax: an automated methodology for generating peak-power traffic in networks-on-chip. NOCS 2016: 1-8 - [e3]Sören Sonntag, Sandro Bartolini, Giorgos Dimitrakopoulos, José M. García:
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2016, Prague, Czech Republic, January 18, 2016. ACM 2016, ISBN 978-1-4503-4084-7 [contents] - 2015
- [j13]Davide Bertozzi, Giorgos Dimitrakopoulos, José Flich, Sören Sonntag:
The fast evolving landscape of on-chip communication - Selected future challenges and research avenues. Des. Autom. Embed. Syst. 19(1-2): 59-76 (2015) - [j12]Ioannis Seitanidis, Anastasios Psarras, Kypros Chrysanthou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 3015-3028 (2015) - [c23]Anastasios Psarras, I. Seitanidis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation. DATE 2015: 1090-1095 - [c22]Alexandros Panteloukas, Anastasios Psarras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
Timing-resilient Network-on-Chip architectures. IOLTS 2015: 77-82 - 2014
- [j11]Davide Bertozzi, Giorgos Dimitrakopoulos, Sören Sonntag:
Editorial. Des. Autom. Embed. Syst. 18(3-4): 119-120 (2014) - [c21]Giorgos Dimitrakopoulos, I. Seitanidis, Anastasios Psarras, K. Tsiouris, Pavlos M. Mattheakis, Jordi Cortadella:
Hardware primitives for the synthesis of multithreaded elastic systems. DATE 2014: 1-4 - [c20]I. Seitanidis, Anastasios Psarras, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos:
ElastiStore: An elastic buffer architecture for Network-on-Chip routers. DATE 2014: 1-6 - [c19]I. Seitanidis, Anastasios Psarras, Emmanouil Kalligeros, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
ElastiNoC: A self-testable distributed VC-based Network-on-Chip architecture. NOCS 2014: 135-142 - [e2]Giorgos Dimitrakopoulos, Sören Sonntag, José Flich, Pascal Vivet:
Proceedings of the 8th International Workshop on Interconnection Network Architecture - On-Chip, Multi-Chip, INA-OCMC 2014, Vienna, Austria, January 22, 2014. ACM 2014, ISBN 978-1-4503-2639-1 [contents] - [e1]Farhad Mehdipour, Giorgos Dimitrakopoulos:
Proceedings of the 2014 International Workshop on Network on Chip Architectures, NoCArc '14, Cambridge, United Kingdom, December 13-14, 2014. ACM 2014, ISBN 978-1-4503-3064-0 [contents] - 2013
- [j10]Giorgos Dimitrakopoulos, Emmanouil Kalligeros, Costas Galanopoulos:
Merged Switch Allocation and Traversal in Network-on-Chip Switches. IEEE Trans. Computers 62(10): 2001-2012 (2013) - [c18]Giorgos Dimitrakopoulos, N. Georgiadis, Chrysostomos Nicopoulos, Emmanouil Kalligeros:
Switch folding: network-on-chip routers with time-multiplexed output ports. DATE 2013: 344-349 - 2012
- [j9]Haridimos T. Vergos, Giorgos Dimitrakopoulos:
On Modulo 2^n+1 Adder Design. IEEE Trans. Computers 61(2): 173-186 (2012) - [j8]Darío Suárez Gracia, Giorgos Dimitrakopoulos, Teresa Monreal Arnal, Manolis Katevenis, Víctor Viñals Yúfera:
LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1510-1523 (2012) - [c17]Giorgos Dimitrakopoulos, Emmanouil Kalligeros:
Dynamic-priority arbiter and multiplexer soft macros for on-chip networks switches. DATE 2012: 542-545 - [c16]Antoni Roca, José Flich, Giorgos Dimitrakopoulos:
DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS. FPL 2012: 394-399 - [c15]Giorgos Dimitrakopoulos, Emmanouil Kalligeros:
Low-cost fault-tolerant switch allocator for network-on-chip routers. INA-OCMC@HiPEAC 2012: 25-28 - 2011
- [c14]Giorgos Dimitrakopoulos, Christoforos Kachris, Emmanouil Kalligeros:
Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks. FPL 2011: 90-96 - [c13]Giorgos Dimitrakopoulos, Kostas Galanopoulos:
Switch allocator for bufferless network-on-chip routers. INA-OCMC@HiPEAC 2011: 19-22
2000 – 2009
- 2009
- [j7]Nikos Chrysos, Giorgos Dimitrakopoulos:
Practical High-Throughput Crossbar Scheduling. IEEE Micro 29(4): 22-35 (2009) - [j6]Yiouli Kritikou, Giorgos Dimitrakopoulos, E. Dimitrellou, Panagiotis Demestichas:
A management scheme for improving transportation efficiency and contributing to the enhancement of the social fabric. Telematics Informatics 26(4): 375-390 (2009) - 2008
- [j5]Giorgos Dimitrakopoulos, Costas Galanopoulos, Christos Mavrokefalidis, Dimitris Nikolos:
Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 837-850 (2008) - [c12]Nikos Chrysos, Giorgos Dimitrakopoulos:
Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation. Hot Interconnects 2008: 67-74 - [c11]Giorgos Dimitrakopoulos, Nikos Chrysos, Costas Galanopoulos:
Fast arbiters for on-chip network switches. ICCD 2008: 664-670 - 2007
- [j4]Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos:
Sorter Based Permutation Units for Media-Enhanced Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 711-715 (2007) - 2006
- [c10]Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos:
An Energy-Delay Efficient Subword Permutation Unit. ASAP 2006: 245-252 - [c9]Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos:
Fast bit permutation unit for media enhanced microprocessors. ISCAS 2006 - 2005
- [j3]Giorgos Dimitrakopoulos, Dimitris Nikolos:
High-Speed Parallel-Prefix VLSI Ling Adders. IEEE Trans. Computers 54(2): 225-231 (2005) - [j2]Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos:
Efficient Diminished-1 Modulo 2^n+1 Multipliers. IEEE Trans. Computers 54(4): 491-496 (2005) - [c8]Giorgos Dimitrakopoulos, Dimitris G. Nikolos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
New architectures for modulo 2N - 1 adders. ICECS 2005: 1-4 - [c7]Giorgos Dimitrakopoulos, Dimitris Nikolos:
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing. PATMOS 2005: 308-317 - 2004
- [j1]Giorgos Dimitrakopoulos, Vassilis Paliouras:
A novel architecture and a systematic graph-based optimization methodology for modulo multiplication. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(2): 354-370 (2004) - [c6]Giorgos Dimitrakopoulos, Pavlos Kolovos, P. Kalogerakis, Dimitris Nikolos:
Design of High-Speed Low-Power Parallel-Prefix VLSI Adders. PATMOS 2004: 248-257 - 2003
- [c5]Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
A Family of Parallel-Pre.x Modulo 2n - 1 Adders. ASAP 2003: 326-336 - [c4]Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos:
Efficient modulo 2n+1 tree multipliers for diminished-1 operands. ICECS 2003: 200-203 - [c3]Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
A systematic methodology for designing area-time efficient parallel-prefix modulo 2n - 1 adders. ISCAS (5) 2003: 225-228 - [c2]Giorgos Dimitrakopoulos, Xrysovalantis Kavousianos, Dimitris Nikolos:
Virtual-scan: a novel approach for software-based self-testing of microprocessors. ISCAS (5) 2003: 237-240 - 2002
- [c1]Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis:
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. IOLTW 2002: 152-157
Coauthor Index
aka: Chrysostomos A. Nicopoulos
aka: Dimitris G. Nikolos
aka: I. Seitanidis
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