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Jason Helge Anderson
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- affiliation: University of Toronto, Canada
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2020 – today
- 2024
- [c110]Tianyi Yu, Omar Ragheb, Stephen Wicklund, Jason Helge Anderson:
MLIR-to-CGRA: A Versatile MLIR-Based Compiler Framework for CGRAs. ASAP 2024: 184-192 - [c109]Salim Khemira, Xinyuan Wang, Anh Nguyen
, Yutaka Tamiya, Makoto Taiji, Takahide Yoshikawa, Jason Helge Anderson:
Raising Compute Density of Molecular Dynamics Simulation Through Approximate Memoization. ASAP 2024: 195-203 - [c108]Omar Ragheb
CLUMAP: Clustered Mapper for CGRAs with Predication. DAC 2024: 101:1-101:6 - [c107]Rami Beidas, Jason Helge Anderson:
Mapping Enumeration for Multi-Context CGRAs Using Zero-Suppressed Binary Decision Diagrams. FCCM 2024: 151-161 - [c106]Haoran Wei
CAD Techniques for NoC-Connected Multi-CGRA Systems. HEART 2024: 109-118 - [c105]Omar Ragheb, Stephen Wicklund, Matthew Walker, Rami Beidas, Adham Ragab, Tianyi Yu, Jason Helge Anderson:
CGRA-ME 2.0: A Research Framework for Next-Generation CGRA Architectures and CAD. IPDPS (Workshops) 2024: 642-649 - 2023
- [c104]Guanglei Zhou, Jason Helge Anderson:
Area-Driven FPGA Logic Synthesis Using Reinforcement Learning. ASP-DAC 2023: 159-165 - [c103]Guanglei Zhou, Mirjana Stojilovic, Jason Helge Anderson:
GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors. FPL 2023: 305-310 - [c102]Omar Ragheb, Rami Beidas, Jason Helge Anderson:
Statically Scheduled vs. Elastic CGRA Architectures: Impact on Mapping Feasibility. IPDPS Workshops 2023: 468-475 - 2022
- [j23]Jianyi Cheng
Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code. IEEE Trans. Computers 71(4): 933-946 (2022) - [c101]Hsuan Hsiao, Joshua San Miguel
Streaming Accuracy: Characterizing Early Termination in Stochastic Computing. ASP-DAC 2022: 320-325 - [c100]Rami Beidas, Jason Helge Anderson:
CGRA Mapping Using Zero-Suppressed Binary Decision Diagrams. ASP-DAC 2022: 616-622 - [c99]Omar Ragheb, Tianyi Yu, David Ma, Jason Helge Anderson:
Modeling and Exploration of Elastic CGRAs. FPL 2022: 404-410 - [c98]Omar Ragheb, Tianyi Yu, Rami Beidas, Jason Helge Anderson:
Elastic Multi-Context CGRAs. IPDPS Workshops 2022: 655-662 - 2021
- [c97]Vimal Chacko, Jason Helge Anderson:
Power, Performance and Area Consequences of Multi-Context Support in CGRAs. ASAP 2021: 49-52 - [c96]Jason Helge Anderson, Rami Beidas, Vimal Chacko, Hsuan Hsiao, Xiaoyi Ling, Omar Ragheb, Xinyuan Wang, Tianyi Yu:
CGRA-ME: An Open-Source Framework for CGRA Architecture and CAD Research : (Invited Paper). ASAP 2021: 156-162 - [c95]Xinyuan Wang, Tianyi Yu, Hsuan Hsiao, Jason Helge Anderson:
Double-Pumping the Interconnect for Area Reduction in Coarse-Grained Reconfigurable Arrays. ASAP 2021: 242-249 - [c94]Hsuan Hsiao, Joshua San Miguel
Zero Correlation Error: A Metric for Finite-Length Bitstream Independence in Stochastic Computing. ASP-DAC 2021: 260-265 - [c93]Omar Ragheb, Jason Helge Anderson:
High-Level Synthesis of Transactional Memory. ASP-DAC 2021: 481-486 - [c92]Xiaoyi Ling, Takahiro Notsu, Jason Helge Anderson:
An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems. DSD 2021: 35-42 - [c91]Jin Hee Kim, Jason Helge Anderson:
Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation. FPL 2021: 334-340 - [c90]Austin Liolli, Omar Ragheb, Jason Helge Anderson:
Profiling-Based Control-Flow Reduction in High-Level Synthesis. FPT 2021: 1-6 - 2020
- [j22]Kevin E. Murray
Optimizing FPGA Logic Block Architectures for Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 28(6): 1378-1391 (2020)
2010 – 2019
- 2019
- [c89]Hyeon Uk Sim, Jason Helge Anderson, Jongeun Lee:
XOMA: exclusive on-chip memory architecture for energy-efficient deep learning acceleration. ASP-DAC 2019: 651-656 - [c88]Hsuan Hsiao, Jason Helge Anderson:
Thread Weaving: Static Resource Scheduling for Multithreaded High-Level Synthesis. DAC 2019: 2 - [c87]Matthew J. P. Walker, Jason Helge Anderson:
Generic Connectivity-Based CGRA Mapping via Integer Linear Programming. FCCM 2019: 65-73 - [c86]Ian Taras, Jason Helge Anderson:
Impact of FPGA Architecture on Area and Performance of CGRA Overlays. FCCM 2019: 87-95 - [c85]Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, George A. Constantinides:
EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. FPGA 2019: 142-151 - [c84]Nicholas V. Giamblanco, Jason Helge Anderson:
A Dynamic Memory Allocation Library for High-Level Synthesis. FPL 2019: 314-320 - [c83]Brett Grady, Jason Helge Anderson:
Physical Design Considerations for Synthesizable Standard-Cell-Based FPGAs. HEART 2019: 3:1-3:6 - [c82]Nicholas V. Giamblanco, Jason Helge Anderson:
ASAP: Automatic Sizing and Partitioning for Dynamic Memory Heaps in High-Level Synthesis. FPT 2019: 275-278 - [c81]Yu Ting Chen, Jin Hee Kim, Kexin Li
High-Level Synthesis Techniques to Generate Deeply Pipelined Circuits for FPGAs with Registered Routing. FPT 2019: 375-378 - [i2]Matthew J. P. Walker, Jason Helge Anderson:
Generic Connectivity-Based CGRA Mapping via Integer Linear Programming. CoRR abs/1901.11129 (2019) - 2018
- [c80]S. Alexander Chin, Jason Helge Anderson:
An architecture-agnostic integer linear programming approach to CGRA mapping. DAC 2018: 128:1-128:6 - [c79]Hsuan Hsiao, Jason Helge Anderson:
Sensei: An area-reduction advisor for FPGA high-level synthesis. DATE 2018: 25-30 - [c78]Samridhi Bansal, Hsuan Hsiao, Tomasz S. Czajkowski, Jason Helge Anderson:
High-level synthesis of software-customizable floating-point cores. DATE 2018: 37-42 - [c77]Omar Ragheb, Jason Helge Anderson:
High-Level Synthesis of FPGA Circuits with Multiple Clock Domains. FCCM 2018: 109-116 - [c76]Jing Chen, Xue Liu, Jason Helge Anderson:
Software-Specified FPGA Accelerators for Elementary Functions. FPT 2018: 54-61 - [c75]Kuang Ping Niu, Jason Helge Anderson:
Compact Area and Performance Modelling for CGRA Architecture Evaluation. FPT 2018: 126-133 - [c74]Jin Hee Kim, Jongeun Lee, Jason Helge Anderson:
FPGA Architecture Enhancements for Efficient BNN Implementation. FPT 2018: 214-221 - [c73]Brett Grady, Jason Helge Anderson:
Synthesizable Heterogeneous FPGA Fabrics. FPT 2018: 222-229 - [c72]Jongsok Choi, Ruolong Lian, Zhi Li, Andrew Canis, Jason Helge Anderson:
Accelerating Memcached on AWS Cloud FPGAs. HEART 2018: 2:1-2:8 - [c71]S. Alexander Chin, Kuang Ping Niu, Matthew J. P. Walker, Shizhang Yin, Alexander Mertens, Jongeun Lee, Jason Helge Anderson:
Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework. ISPD 2018: 48-55 - [e3]Jason Helge Anderson, Kia Bazargan:
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2018, Monterey, CA, USA, February 25-27, 2018. ACM 2018 [contents] - [i1]Jin Hee Kim, Brett Grady, Ruolong Lian, John Brothers, Jason Helge Anderson:
FPGA-Based CNN Inference Accelerator Synthesized from Multi-Threaded C Software. CoRR abs/1807.10695 (2018) - 2017
- [j21]Noriaki Sakamoto, Tanvir Ahmed
Subleq⊝: An Area-Efficient Two-Instruction-Set Computer. IEEE Embed. Syst. Lett. 9(2): 33-36 (2017) - [j20]Jin Hee Kim, Jason Helge Anderson:
Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow. ACM Trans. Reconfigurable Technol. Syst. 10(2): 11:1-11:23 (2017) - [j19]Philip Heng Wai Leong
The First 25 Years of the FPL Conference: Significant Papers. ACM Trans. Reconfigurable Technol. Syst. 10(2): 15:1-15:17 (2017) - [j18]Charles Eric LaForest, Jason Helge Anderson:
Microarchitectural Comparison of the MXP and Octavo Soft-Processor FPGA Overlays. ACM Trans. Reconfigurable Technol. Syst. 10(3): 19:1-19:25 (2017) - [j17]Safeen Huda
Leveraging Unused Resources for Energy Optimization of FPGA Interconnect. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2307-2320 (2017) - [j16]Jongsok Choi
From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2867-2880 (2017) - [c70]S. Alexander Chin, Noriaki Sakamoto, Allan Rui, Jim Zhao, Jin Hee Kim, Yuko Hara-Azumi, Jason Helge Anderson:
CGRA-ME: A unified framework for CGRA modelling and exploration. ASAP 2017: 184-189 - [c69]Yu Ting Chen, Jason Helge Anderson:
Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software. FPL 2017: 1-8 - [c68]Jin Hee Kim, Brett Grady, Ruolong Lian, John Brothers, Jason Helge Anderson:
FPGA-based CNN inference accelerator synthesized from multi-threaded C software. SoCC 2017: 268-273 - [e2]Jonathan W. Greene, Jason Helge Anderson:
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2017, Monterey, CA, USA, February 22-24, 2017. ACM 2017, ISBN 978-1-4503-4354-1 [contents] - 2016
- [j15]Razvan Nane
A Survey and Evaluation of FPGA High-Level Synthesis Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1591-1604 (2016) - [j14]S. Alexander Chin, Jason Luu, Safeen Huda, Jason Helge Anderson:
Hybrid LUT/Multiplexer FPGA Logic Architectures. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1280-1292 (2016) - [c67]Jongsok Choi, Ruolong Lian, Stephen Dean Brown, Jason Helge Anderson:
A unified software approach to specify pipeline and spatial parallelism in FPGA hardware. ASAP 2016: 75-82 - [c66]Jason Helge Anderson, Yuko Hara-Azumi, Shigeru Yamashita:
Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy. DATE 2016: 1550-1555 - [c65]Safeen Huda, Jason Helge Anderson:
Towards PVT-Tolerant Glitch-Free Operation in FPGAs. FPGA 2016: 90-99 - [c64]Paolo Ienne, Walid A. Najjar
Preface. FPL 2016: 1 - [c63]Jason Helge Anderson:
High-level synthesis - the right side of history. FPT 2016: 1 - [c62]Safeen Huda, Jason Helge Anderson:
Power Optimization of FPGA Interconnect Via Circuit and CAD Techniques. ISPD 2016: 123-130 - [p1]Andrew Canis, Jongsok Choi, Blair Fort, Bain Syrowik, Ruolong Lian, Yu Ting Chen, Hsuan Hsiao, Jeffrey B. Goeders, Stephen Dean Brown, Jason Helge Anderson:
LegUp High-Level Synthesis. FPGAs for Software Programmers 2016: 175-190 - [e1]Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele:
26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016. IEEE 2016, ISBN 978-2-8399-1844-2 [contents] - 2015
- [j13]Qijing Huang
The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware. ACM Trans. Reconfigurable Technol. Syst. 8(3): 14:1-14:26 (2015) - [c61]Stefan Hadjis, Andrew Canis, Ryoya Sobue, Yuko Hara-Azumi, Hiroyuki Tomiyama, Jason Helge Anderson:
Profiling-driven multi-cycling in FPGA high-level synthesis. DATE 2015: 31-36 - [c60]Tanvir Ahmed
Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC. EUC 2015: 114-123 - [c59]Jin Hee Kim, Jason Helge Anderson:
Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow. FPL 2015: 1-8 - [c58]Philip Heng Wai Leong
Significant papers from the first 25 years of the FPL conference. FPL 2015: 1-3 - [c57]Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson:
Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware. FPT 2015: 152-159 - 2014
- [j12]Jason Luu, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr, Sen Wang, Tim Liu, Nooruddin Ahmed, Kenneth B. Kent
VTR 7.0: Next Generation Architecture and CAD System for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 7(2): 6:1-6:30 (2014) - [j11]Jason Helge Anderson, Kiyoung Choi:
Introduction to the Special Issue on the 11th International Conference on Field-Programmable Technology (FPT'12). ACM Trans. Reconfigurable Technol. Syst. 7(3): 18:1-18:2 (2014) - [c56]Tahir Diop, Natalie D. Enright Jerger, Jason Helge Anderson:
Power Modeling for Heterogeneous Processors. GPGPU@ASPLOS 2014: 90 - [c55]Blair Fort, Andrew Canis, Jongsok Choi, Nazanin Calagar, Ruolong Lian, Stefan Hadjis, Yu Ting Chen, Mathew Hall, Bain Syrowik, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson:
Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis. EUC 2014: 120-129 - [c54]Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent
On Hard Adders and Carry Chains in FPGAs. FCCM 2014: 52-59 - [c53]Safeen Huda, Jason Helge Anderson, Hirotaka Tamura:
Optimizing effective interconnect capacitance for FPGA power reduction. FPGA 2014: 11-20 - [c52]Jason Luu, Jonathan Rose, Jason Helge Anderson:
Towards interconnect-adaptive packing for FPGAs. FPGA 2014: 21-30 - [c51]Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson:
Source-level debugging for FPGA high-level synthesis. FPL 2014: 1-8 - [c50]Andrew Canis, Stephen Dean Brown, Jason Helge Anderson:
Modulo SDC scheduling with recurrence minimization in high-level synthesis. FPL 2014: 1-8 - [c49]Marcel Gort, Jason Helge Anderson:
Design re-use for compile time reduction in FPGA high-level synthesis flows. FPT 2014: 4-11 - [c48]Charles Eric LaForest, Jason Helge Anderson, J. Gregory Steffan:
Approaching overhead-free execution on FPGA soft-processors. FPT 2014: 99-106 - 2013
- [j10]Bill Teng, Jason Helge Anderson:
Latch-Based Performance Optimization for Field-Programmable Gate Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 667-680 (2013) - [j9]Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson:
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems. ACM Trans. Embed. Comput. Syst. 13(2): 24:1-24:27 (2013) - [j8]Marcel Gort, Jason Helge Anderson:
Combined Architecture/Algorithm Approach to Fast FPGA Routing. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1067-1079 (2013) - [c47]Marcel Gort, Jason Helge Anderson:
Range and bitmask analysis for hardware optimization in high-level synthesis. ASP-DAC 2013: 773-779 - [c46]Andrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang
From software to accelerators with LegUp high-level synthesis. CASES 2013: 18:1-18:9 - [c45]Andrew Canis, Jason Helge Anderson, Stephen Dean Brown:
Multi-pumping for resource reduction in FPGA high-level synthesis. DATE 2013: 194-197 - [c44]Qijing Huang
The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs. FCCM 2013: 89-96 - [c43]Jason Helge Anderson, Stephen Dean Brown, Andrew Canis, Jongsok Choi:
High-level synthesis with LegUp: a crash course for users and researchers. FPGA 2013: 7-8 - [c42]Safeen Huda, Jason Helge Anderson, Hirotaka Tamura:
Charge recycling for power reduction in FPGA interconnect. FPL 2013: 1-8 - [c41]S. Alexander Chin, Jason Helge Anderson:
A case for hardened multiplexers in FPGAs. FPT 2013: 42-49 - [c40]Ana Klimovic
Bitwidth-optimized hardware accelerators with software fallback. FPT 2013: 136-143 - [c39]Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson:
From software threads to parallel hardware in high-level synthesis for FPGAs. FPT 2013: 270-277 - [c38]Jiu Cheng Cai, Ruolong Lian, Mengyao Wang, Andrew Canis, Jongsok Choi, Blair Fort, Eric Hart, Emily Miao, Yanyan Zhang, Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson:
From C to Blokus Duo with LegUp high-level synthesis. FPT 2013: 486-489 - [c37]Tahir Diop, Steven Gurfinkel, Jason Helge Anderson, Natalie D. Enright Jerger
DistCL: A Framework for the Distributed Execution of OpenCL Kernels. MASCOTS 2013: 556-566 - [c36]Edgar Mora-Sanchez, Jason Helge Anderson:
Leakage power reduction in FPGA DSP circuits through algorithmic noise tolerance. ReConFig 2013: 1-6 - 2012
- [j7]Marcel Gort, Jason Helge Anderson:
Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(1): 61-74 (2012) - [j6]Chirag Ravishankar, Jason Helge Anderson, Andrew A. Kennings:
FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(9): 1305-1318 (2012) - [j5]Jason Helge Anderson, Qiang Wang, Chirag Ravishankar:
Raising FPGA Logic Density Through Synthesis-Inspired Architecture. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 537-550 (2012) - [c35]Zissis Poulos, Yu-Shen Yang, Jason Helge Anderson, Andreas G. Veneris, Bao Le:
Leveraging reconfigurability to raise productivity in FPGA functional debug. DATE 2012: 292-295 - [c34]Jongsok Choi, Kevin Nam, Andrew Canis, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski:
Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems. FCCM 2012: 17-24 - [c33]Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent
The VTR project: architecture and CAD for FPGAs from verilog to routing. FPGA 2012: 77-86 - [c32]Warren Wai-Kit Shum, Jason Helge Anderson:
Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power. FPGA 2012: 107-110 - [c31]Stefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Dean Brown, Tomasz S. Czajkowski:
Impact of FPGA architecture on resource sharing in high-level synthesis. FPGA 2012: 111-114 - [c30]Marcel Gort, Jason Helge Anderson:
Analytical placement for heterogeneous FPGAs. FPL 2012: 143-150 - [c29]Chirag Ravishankar, Andrew A. Kennings, Jason Helge Anderson:
FPGA power reduction by guarded evaluation considering physical information. VLSI-SoC 2012: 271-274 - 2011
- [c28]Mark Aldham, Jason Helge Anderson, Stephen Dean Brown, Andrew Canis:
Low-cost hardware profiling of run-time and energy in FPGA embedded processors. ASAP 2011: 61-68 - [c27]Jason Helge Anderson, Qiang Wang:
Area-efficient FPGA logic elements: Architecture and synthesis. ASP-DAC 2011: 369-375 - [c26]Alireza Rakhshanfar, Jason Helge Anderson:
An integer programming placement approach to FPGA clock power reduction. ASP-DAC 2011: 831-836 - [c25]Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski:
LegUp: high-level synthesis for FPGA-based processor/accelerator systems. FPGA 2011: 33-36 - [c24]Jason Luu, Jason Helge Anderson, Jonathan Rose:
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. FPGA 2011: 227-236 - [c23]Bill Teng, Jason Helge Anderson:
Latch-Based Performance Optimization for FPGAs. FPL 2011: 58-63 - [c22]Marcel Gort, Jason Helge Anderson:
Reducing FPGA Router Run-Time through Algorithm and Architecture. FPL 2011: 336-342 - [c21]Warren Wai-Kit Shum, Jason Helge Anderson:
FPGA glitch power analysis and reduction. ISLPED 2011: 27-32 - 2010
- [c20]Jason Helge Anderson:
A PUF design for secure FPGA-based embedded systems. ASP-DAC 2010: 1-6 - [c19]Jason Helge Anderson, Chirag Ravishankar:
FPGA power reduction by guarded evaluation. FPGA 2010: 157-166 - [c18]Steven Birk, J. Gregory Steffan, Jason Helge Anderson:
Parallelizing FPGA placement using Transactional Memory. FPT 2010: 61-69 - [c17]Marcel Gort, Jason Helge Anderson:
Deterministic multi-core parallel routing for FPGAs. FPT 2010: 78-86
2000 – 2009
- 2009
- [j4]Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson:
Packing Techniques for Virtex-5 FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(3): 18:1-18:24 (2009) - [j3]Jason Helge Anderson, Farid N. Najm:
Low-Power Programmable FPGA Routing Circuitry. IEEE Trans. Very Large Scale Integr. Syst. 17(8): 1048-1060 (2009) - [c16]Jason Helge Anderson:
Emerging application domains: research challenges and opportunities for FPGAs. FPGA 2009: 1-2 - [c15]Qiang Wang, Subodh Gupta, Jason Helge Anderson:
Clock power reduction for virtex-5 FPGAs. FPGA 2009: 13-22 - [c14]Jason Helge Anderson, Qiang Wang:
Improving logic density through synthesis-inspired architecture. FPL 2009: 105-111 - [c13]Safeen Huda, Muntasir Mallick, Jason Helge Anderson:
Clock gating architectures for FPGA power reduction. FPL 2009: 112-118 - 2008
- [c12]Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal:
Architecture-specific packing for virtex-5 FPGAs. FPGA 2008: 5-13 - 2007
- [c11]Subodh Gupta, Jason Helge Anderson, Linda Farragher, Qiang Wang:
CAD Techniques for Power Optimization in Virtex-5 FPGAs. CICC 2007: 85-88 - 2006
- [j2]Jason Helge Anderson, Farid N. Najm:
Active leakage power optimization for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 423-437 (2006) - 2004
- [j1]Jason Helge Anderson, Farid N. Najm:
Power estimation techniques for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1015-1027 (2004) - [c10]Jason Helge Anderson, Farid N. Najm:
Interconnect capacitance estimation for FPGAs. ASP-DAC 2004: 713-718 - [c9]Jason Helge Anderson, Farid N. Najm:
A novel low-power FPGA routing switch. CICC 2004: 719-722 - [c8]Jason Helge Anderson, Farid N. Najm, Tim Tuan:
Active leakage power optimization for FPGAs. FPGA 2004: 33-41 - [c7]Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng:
Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis. FPL 2004: 168-178 - [c6]Jason Helge Anderson, Farid N. Najm:
Low-power programmable routing circuitry for FPGAs. ICCAD 2004: 602-609 - 2003
- [c5]Jason Helge Anderson, Farid N. Najm:
Switching activity analysis and pre-layout activity prediction for FPGAs. SLIP 2003: 15-21 - 2002
- [c4]Jason Helge Anderson, Farid N. Najm:
Power-aware technology mapping for LUT-based FPGAs. FPT 2002: 211-218 - 2000
- [c3]Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman:
A Placement Algorithm for FPGA Designs with Multiple I/O Standards. FPL 2000: 211-220
1990 – 1999
- 1998
- [c2]Jason Helge Anderson, Stephen Dean Brown:
Technology Mapping for Large Complex PLDs. DAC 1998: 698-703 - [c1]Jason Helge Anderson, Stephen Dean Brown:
An LPGA with Foldable PLA-style Logic Blocks. FPGA 1998: 244-252
Coauthor Index
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