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DSD 2010: Lille, France
- Sebastián López:
13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France. IEEE Computer Society 2010, ISBN 978-0-7695-4171-6
System and Circuit Synthesis (1)
- Levent Aksoy
, Eduardo Costa
Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications. 3-10 - Toktam Taghavi, Andy D. Pimentel
Visualization of Multi-objective Design Space Exploration for Embedded Systems. 11-20 - Alice M. Tokarnia, Marina Tachibana:
Design of Trace-Based Split Array Caches for Embedded Applications. 21-27 - Jian Wang, Joar Sohl, Olof Kraigher, Dake Liu:
Software Programmable Data Allocation in Multi-bank Memory of SIMD Processors. 28-33
Systems and Networks on Chip (1)
- Maurizio Palesi, Rickard Holsmark, Xiaohang Wang, Shashi Kumar, Mei Yang, Yingtao Jiang, Vincenzo Catania:
An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip. 37-44 - Nastaran Salehi, Ahmad Khadem Zadeh, Arash Dana:
Power Distribution in NoCs Through a Fuzzy Based Selection Strategy for Adaptive Routing. 45-52 - Tim Kranich, Mladen Berekovic
NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems. 53-59 - Son Truong Nguyen, Shigeru Oyanagi:
A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-chip Networks. 60-67
Reconfigurable Computing (1)
- Basher Shehan, Ralf Jahr, Sascha Uhrig, Theo Ungerer:
Reconfigurable Grid Alu Processor: Optimization and Design Space Exploration. 71-79 - Miguel Lino Silva, João Canas Ferreira
Creation of Partial FPGA Configurations at Run-Time. 80-87 - Andrés Otero
A Modular Peripheral to Support Self-Reconfiguration in SoCs. 88-95 - Rubén Salvador
High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs. 96-103
System-Level Energy Optimization of HW/SW Embedded Systems
- Kees Goossens, Dongrui She, Aleksandar Milutinovic, Anca Mariana Molnos:
Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications. 107-114 - Jing Cao, Albert Nymeyer:
A Markov Model for Low-Power High-Fidelity Design-Space Exploration. 115-122 - Fernando Pescador, Eduardo Juárez Martínez
A Test Bench for Distortion-Energy Optimization of a DSP-Based H.264/SVC Decoder. 123-129 - Stanislaw J. Piestrak:
On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels. 133-140
System and Circuit Synthesis (2)
- Dennis Bode, Mladen Berekovic
QoR Analysis of Automated Clock-Mesh Implementation under OCV Consideration. 141-146 - Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Kunal P. Ghosh, Kavi Arya, Madhav P. Desai:
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems. 147-154 - Igor Lemberski, Petr Fiser:
Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints. 155-162
Systems and Networks on Chip (2)
- Antoni Roca, José Flich
A Latency-Efficient Router Architecture for CMP Systems. 165-172 - Claas Cornelius, Philipp Gorski, Stephan Kubisch, Dirk Timmermann
Trading Hardware Overhead for Communication Performance in Mesh-Type Topologies. 173-180 - Saad Mubeen
Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms. 181-188
Multicore Systems: Design and Applications (1)
- Andrea Marongiu, Paolo Burgio
Evaluating OpenMP Support Costs on MPSoCs. 191-198 - Pierfrancesco Foglia
Re-NUCA: Boosting CMP Performance Through Block Replication. 199-206 - Ana Bosque, Víctor Viñals
Filtering Directory Lookups in CMPs. 207-216
Fault Tolerance in Digital System Design (1)
- Marcus Jeitler, Jakob Lechner:
Low Latency Recovery from Transient Faults for Pipelined Processor Architectures. 219-225 - Stefan Frehse, Görschwin Fey
RobuCheck: A Robustness Checker for Digital Circuits. 226-231 - Makoto Sugihara:
Dynamic Control Flow Checking Technique for Reliable Microprocessors. 232-239
Posters
- Pedro Miguens Matutino
Arithmetic Units for RNS Moduli {2n-3} and {2n+3} Operations. 243-246 - Dan Hotoleanu, Octavian Cret, Alin Suciu, Tamas Györfi, Lucia Vacariu:
Real-Time Testing of True Random Number Generators Through Dynamic Reconfiguration. 247-250 - Subayal Khan, Kari Tiensyrjä, Jari Nurmi
Instantiating GENESYS Application Architecture Modeling via UML 2.0 Constructs and MARTE Profile. 251-254 - Tobias Lange, Naim Harb, Haisheng Liu, Smaïl Niar, Rabie Ben Atitallah:
An Improved Automotive Multiple Target Tracking System Design. 255-258 - Lara G. Villanueva, Gustavo Marrero Callicó, Félix Tobajas
Medical Diagnosis Improvement Through Image Quality Enhancement Based on Super-Resolution. 259-262 - Zdenek Prikryl, Karel Masarík, Tomás Hruska, Adam Husár:
Generated Cycle-Accurate Profiler for C Language. 263-268 - Mostafa E. Salehi
Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications. 269-272
System, Hardware and Embedded-Software Specification, Modeling, Verification and Test (1)
- José Luis Risco-Martín
Simulation of High-Performance Memory Allocators. 275-282 - René Kothe, Heinrich Theodor Vierhaus:
Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures. 283-290 - Franco Fummi, Giovanni Perbellini, Davide Quaglia
Exploration of Network Alternatives for Middleware-centric Embedded System Design. 291-297
Flexible Digital Radio
- Marcel D. van de Burgwal, Kenneth C. Rovers, Koen C. H. Blom, André B. J. Kokkeler, Gerard J. M. Smit:
Adaptive Beamforming Using the Reconfigurable MONTIUM TP. 301-308 - Malek Naoues, Laurent Alaus, Dominique Noguet:
A Common Operator for FFT and Viterbi Algorithms. 309-313 - Ismael Gómez, Massimo Camatel, Jordi Bracke, Vuk Marojevic, Antoni Gelonch, Fabrizio Vacca, Guido Masera
ALOE-Based Flexible LDPC Decoder. 314-320 - Adolfo Recio
Physical Layer for Spectrum-Aware Reconfigurable OFDM on an FPGA. 321-327
Multicore Systems: Design and Applications (2)
- Sonia López, Oscar Garnica
Adaptive Cache Memories for SMT Processors. 331-338 - Frank Reichenbach, Alexander Wold:
Multi-core Technology -- Next Evolution Step in Safety Critical Systems for Industrial Applications? 339-346 - Cor Meenderinck, Ben H. H. Juurlink:
A Case for Hardware Task Management Support for the StarSS Programming Model. 347-354 - George Kornaros
On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on Reconfigurable Platforms. 355-362
Fault Tolerance in Digital System Design (2)
- Martin Straka, Jan Kastil
Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration. 365-372 - Ronaldo Rodrigues Ferreira, Álvaro Freitas Moreira, Luigi Carro
System Level Hardening by Computing with Matrices. 373-379 - Jaroslav Borecký, Martin Kohlík, Hana Kubátová, Pavel Kubalík:
Faults Coverage Improvement Based on Fault Simulation and Partial Duplication. 380-386
Posters
- Masaru Takesue:
A Class of Recursive Networks on a Chip for Enhancing Intercluster Parallelism. 389-392 - Yun Jie Wu, Dominique Houzet, Sylvain Huet:
A Programming Model and a NoC-Based Architecture for Streaming Applications. 393-397 - Somayyeh Koohi, Alireza Shafaei, Shaahin Hessabi:
Scalable Architecture for Wavelength-Switched Optical NoC with Multicasting Capability. 398-403 - Deepak Kumar, Pankaj Kumar, Manisha Pattanaik:
Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application. 404-407 - Dimitris Bakalis
Area-Efficient Multi-moduli Squarers for RNS. 408-411 - Ye Gao, Ryusuke Egawa, Hiroyuki Takizawa
A Load-Forwarding Mechanism for the Vector Architecture in Multimedia Applications. 412-415 - Paris Kitsos
Low Power FPGA Implementations of 256-bit Luffa Hash Function. 416-419 - Tsutomu Sasao:
On the Numbers of Variables to Represent Multi-valued Incompletely Specified Functions. 420-423
System and Circuit Synthesis (3)
- Somsubhra Talapatra, Hafizur Rahaman
Unified Digit Serial Systolic Montgomery Multiplication Architecture for Special Classes of Polynomials over GF(2m). 427-432 - Shohreh Sharif Mansouri, Elena Dubrova:
An Improved Hardware Implementation of the Grain Stream Cipher. 433-440 - Luis A. Tarazona, Doug A. Edwards, Andrew Bardsley, Luis A. Plana
Description-Level Optimisation of Synthesisable Asynchronous Circuits. 441-448 - Craig Moore, Wim Meeus, Harald Devos, Dirk Stroobandt:
A Parallel for Loop Memory Template for a High Level Synthesis Compiler. 449-455
Systems and Networks on Chip (3)
- Vrishali Vijay Nimbalkar, Kuruvilla Varghese:
In-channel Flow Control Scheme for Network-on-Chip. 459-466 - Ahmad Patooghy
An Efficient Method to Reliable Data Transmission in Network-on-Chips. 467-474 - Marta Stepniewska, Adam Luczak, Jakub Siast
Network-on-Multi-Chip (NoMC) for Multi-FPGA Multimedia Systems. 475-481 - Julio Dondo
Persistence Management Model for Dynamically Reconfigurable Hardware. 482-489
Wireless Sensor Networks
- Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys
System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes. 493-500 - Ricardo Severino
A Traffic Differentiation Add-On to the IEEE 802.15.4 Protocol: Implementation and Experimental Validation over a Real-Time Operating system. 501-508 - Felipe Lavratti, Alex R. Pinto
Evaluating a Transmission Power Self-Optimization Technique for WSN in EMI Environments. 509-515
Dependability and Testing of Digital Systems (1)
- Palanichamy Manikandan
Path-Delay Fault Testing in Embedded Content Addressable Memories. 519-524 - Martin Rozkovec
Application Dependent FPGA Testing Method. 525-530 - Xiao Zhang
On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism. 531-537
System and Circuit Synthesis (4)
- Enrique Barajas
Behavioural Modelling of DLLs for Fast Simulation and Optimisation of Jitter and Power Consumption. 541-547 - Sander Stuijk
A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic Behaviour. 548-555 - Félix Moreno, Ignacio López, Ricardo Sanz:
A Design Process for Hardware/Software System Co-design and its Application to Designing a Reconfigurable FPGA. 556-562 - Phillip David Ferguson, Aristides Efthymiou
Optimising Self-Timed FPGA Circuits. 563-570
Systems and Networks on Chip (4)
- Nicolas Roudel, François Berry, Jocelyn Sérot, Laurent Eck:
A New High-Level Methodology for Programming FPGA-Based Smart Camera. 573-578 - Andrea Castagnetti, Cécile Belleudy, Sébastien Bilavarn, Michel Auguin:
Power Consumption Modeling for DVFS Exploitation. 579-586 - Christian Bachmann
Automated Power Characterization for Run-Time Power Emulation of SoC Designs. 587-594 - Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides:
Customizable Composition and Parameterization of Hardware Design Transformations. 595-602
Emerging Technologies
- Robert Hartl, Andreas J. Rohatschek, Walter Stechele, Andreas Herkersdorf:
Architectural Vulnerability Factor Estimation with Backwards Analysis. 605-612 - Bibhash Sen
Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit. 613-620 - Juan Núñez
Evaluation of RTD-CMOS Logic Gates. 621-627 - Allen Chen, Ryan Hoppal, Tom Chen:
On CMOS Memory Design in Low Supply Voltage for Integrated Biosensor Applications. 628-634
Dependability and Testing of Digital Systems (2)
- Luca Amati, Cristiana Bolchini
A Formal Condition to Stop an Incremental Automatic Functional Diagnosis. 637-643 - Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel
The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. 644-651 - J. F. Tarillo, Nikolaos Mavrogiannakis, Carlos Arthur Lang Lisbôa, Costas Argyrides, Luigi Carro
Multiple Bit Error Detection and Correction in Memory. 652-657 - Dmitri Mironov
Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. 658-663
System and Circuit Synthesis (5)
- Florent Berthelot, François Charot, Charles Wagner, Christophe Wolinski:
Design Methodology for a High Performance Robust DVB-S2 Decoder Implementation. 667-674 - Muhammad Waqar Azhar
Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor. 675-680 - Zhufei Chu
A Memetic Approach for Nanoscale Hybrid Circuit Cell Mapping. 681-688 - Tingcong Ye, Dilip P. Vasudevan, Jiaoyan Chen, Emanuel M. Popovici, Michel P. Schellekens:
Static Average Case Power Estimation Technique for Block Ciphers. 689-696
System, Hardware and Embedded-Software Specification, Modeling, Verification and Test (2)
- Jochem H. Rutgers, Pascal T. Wolkotte, Philip K. F. Hölzenspies, Jan Kuper, Gerard J. M. Smit:
An Approximate Maximum Common Subgraph Algorithm for Large Digital Circuits. 699-705 - Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser:
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis. 706-713 - Christiaan Baaij, Matthijs Kooijman, Jan Kuper, Arjan Boeijink, Marco Gerards
C?aSH: Structural Descriptions of Synchronous Hardware Using Haskell. 714-721 - Mohammad Salehi, Amirali Baniasadi:
Storage-Aware Value Prediction. 722-728
Applications of (Embedded) Digital Systems
- Ozgur Tasdizen, Ilker Hamzaoglu:
Computation Reduction Techniques for Vector Median Filtering and their Hardware Implementation. 731-736 - Bin Wu, Guido Masera
A Novel VLSI Architecture of Fixed-Complexity Sphere Decoder. 737-744 - Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Packet Classifier Using a Parallel Branching Program Machine. 745-752 - Yusuf Adibelli, Mustafa Parlak, Ilker Hamzaoglu:
A Computation and Power Reduction Technique for H.264 Intra Prediction. 753-760
Reconfigurable Computing (2)
- Imtiaz Sajid, Sotirios G. Ziavras
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance. 763-770 - Barend van Liempd, Daniel Herrera, Miguel E. Figueroa
An FPGA-Based Accelerator for Analog VLSI Artificial Neural Network Emulation. 771-778 - Giovanni Danese, Mauro Giachero, Francesco Leporati, Nelson Nazzicari:
A Multicore Embedded Processor for Fingerprint Recognition. 779-784 - Elias Baaklini, Hassan Sbeity, Smaïl Niar, Nouhad Amaneddine:
H.264 Color Components Video Decoding Parallelization on Multi-core Processors. 785-790
Posters
- Majd Ghazi Batarseh, Ehab Shobaki, Xiang Fang, Haibing Hu, Issa Batarseh
New Digital Control Technique for Improving Transient Response in DC - DC Converters. 793-796 - Mahdi Fazeli
A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits. 797-800 - Pedro Suárez-Casal
A Multicore SDR Architecture for Reconfigurable WiMAX Downlink. 801-804 - Jiri Balcarek, Petr Fiser, Jan Schmidt:
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG. 805-808 - Richard Ruzicka:
Gracefully Degrading Circuit Controllers Based on Polytronics. 809-812 - Antonio da Silva
LEON3 ViP: A Virtual Platform with Fault Injection Capabilities. 813-816 - Jan Balach, Ondrej Novák:
Reconfigurable Fault-Tolerant System Sychronization. 817-820
36th EUROMICRO Conference on Software Engineering and Advanced Applications
- Yi He, Ju Ren, Mei Wen, Qianming Yang, Nan Wu, Chunyuan Zhang:
Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels. 823-830
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