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Víctor Viñals
Víctor Viñals Yúfera
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2020 – today
- 2024
- [i3]Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matías, Luis Piñuel, Teresa Monreal, José María Llabería:
Reuse Detector: Improving the Management of STT-RAM SLLCs. CoRR abs/2402.00533 (2024) - 2023
- [j30]Agustín Navarro-Torres, Jesús Alastruey-Benedé
, Pablo Ibáñez, Víctor Viñals Yúfera:
BALANCER: bandwidth allocation and cache partitioning for multicore processors. J. Supercomput. 79(9): 10252-10276 (2023) - [c42]Carlos Escuin, Asif Ali Khan, Pablo Ibáñez, Teresa Monreal, Jerónimo Castrillón, Víctor Viñals:
Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs. HPCA 2023: 179-192 - [c41]Carlos Escuin, Fernando García-Redondo
MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. ICECS 2023: 1-5 - 2022
- [c40]Darío Suárez Gracia
peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter. DCIS 2022: 1-6 - [c39]Carlos Escuin, Asif Ali Khan, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, Jerónimo Castrillón:
HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches. DroneSE/RAPIDO@HiPEAC 2022: 53-58 - [c38]Agustín Navarro-Torres
Berti: an Accurate Local-Delta Data Prefetcher. MICRO 2022: 975-991 - [i2]Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals:
Forecasting lifetime and performance of a novel NVM last-level cache with compression. CoRR abs/2204.03512 (2022) - [i1]Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals:
L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime. CoRR abs/2204.09504 (2022) - 2021
- [j29]Juan Segarra
A generic framework to integrate data caches in the WCET analysis of real-time systems. J. Syst. Archit. 120: 102304 (2021) - [j28]Javier Díaz, Pablo Ibáñez
Near-optimal replacement policies for shared caches in multicore processors. J. Supercomput. 77(10): 11756-11785 (2021) - 2020
- [j27]Juan Segarra
Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches. IEEE Access 8: 192379-192392 (2020) - [j26]Jose Manuel Herruzo, Sonia González-Navarro
Accelerating Sequence Alignments Based on FM-Index Using the Intel KNL Processor. IEEE ACM Trans. Comput. Biol. Bioinform. 17(4): 1093-1104 (2020)
2010 – 2019
- 2019
- [j25]Alexandra Ferrerón-Labari, Jesús Alastruey-Benedé
A fault-tolerant last level cache for CMPs operating at ultra-low voltage. J. Parallel Distributed Comput. 125: 31-44 (2019) - [j24]Javier Díaz, Teresa Monreal
ReD: A reuse detector for content selection in exclusive shared last-level caches. J. Parallel Distributed Comput. 125: 106-120 (2019) - [c37]Jose Manuel Herruzo, Sonia González-Navarro
Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding. DCC 2019: 577 - [c36]Alejandro Valero
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. WCAE@ISCA 2019: 5:1-5:8 - 2018
- [j23]Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro
Reuse Detector: Improving the Management of STT-RAM SLLCs. Comput. J. 61(6): 856-880 (2018) - 2017
- [j22]Marta Ortín-Obón
Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 2081-2094 (2017) - [c35]Marta Ortín-Obón
A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings. ASP-DAC 2017: 300-305 - 2016
- [j21]Marta Ortín-Obón
Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs. J. Parallel Distributed Comput. 95: 57-68 (2016) - [j20]Marta Ortín-Obón
Analysis of network-on-chip topologies for cost-efficient chip multiprocessors. Microprocess. Microsystems 42: 24-36 (2016) - 2015
- [j19]Ruben Gran
A predictable hardware to exploit temporal reuse in real-time and embedded systems. J. Syst. Archit. 61(5-6): 227-238 (2015) - [j18]Juan Segarra
ACDC: Small, Predictable and High-Performance Data Cache. ACM Trans. Embed. Comput. Syst. 14(2): 38:1-38:26 (2015) - [c34]Marta Ortín
Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization. SiPhotonics@HiPEAC 2015: 17-24 - 2014
- [j17]Marta Ortín-Obón
Capturing the sensitivity of optical network quality metrics to its network interface parameters. Concurr. Comput. Pract. Exp. 26(15): 2504-2517 (2014) - [j16]Darío Suárez Gracia, Alexandra Ferrerón-Labari, Luis Montesano Del Campo, Teresa Monreal Arnal, Víctor Viñals Yúfera
Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping. ACM Trans. Archit. Code Optim. 11(2): 19:1-19:26 (2014) - [c33]Marta Ortín, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals:
Dynamic construction of circuits for reactive traffic in homogeneous CMPs. DATE 2014: 1-4 - [c32]Marta Ortín-Obón
A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip. ACM Great Lakes Symposium on VLSI 2014: 267-272 - [c31]Marco Balboni, Marta Ortín-Obón, Alessandro Capotondi
Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain. NOCS 2014: 72-79 - [c30]Alexandra Ferrerón-Labari, Darío Suárez Gracia
Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages. SBAC-PAD 2014: 238-245 - 2013
- [j15]Ruben Gran Tejero
Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems. J. Syst. Archit. 59(9): 667-678 (2013) - [j14]Jorge Albericio, Pablo Ibáñez
Exploiting reuse locality on inclusive shared last-level caches. ACM Trans. Archit. Code Optim. 9(4): 38:1-38:19 (2013) - [c29]Alexandra Ferrerón-Labari, Marta Ortín-Obón
Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors. ARCS 2013: 256-267 - [c28]Marta Ortín
Characterization and cost-efficient selection of NoC topologies for general purpose CMPs. INA-OCMC@HiPEAC 2013: 21-24 - [c27]Jorge Albericio, Pablo Ibáñez
The reuse cache: downsizing the shared last-level cache. MICRO 2013: 310-321 - 2012
- [j13]Benjamín Sahelices
Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers. J. Comput. Sci. Technol. 27(1): 75-91 (2012) - [j12]Jorge Albericio, Ruben Gran Tejero
ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache. ACM Trans. Archit. Code Optim. 8(4): 19:1-19:20 (2012) - [j11]Darío Suárez Gracia
LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1510-1523 (2012) - [c26]Juan Segarra
A Small and Effective Data Cache for Real-Time Multitasking Systems. IEEE Real-Time and Embedded Technology and Applications Symposium 2012: 45-54 - 2011
- [j10]Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals:
Multi-level Adaptive Prefetching based on Performance Gradient Tracking. J. Instr. Level Parallelism 13 (2011) - [j9]Luis C. Aparicio, Juan Segarra
Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems. J. Syst. Archit. 57(7): 695-706 (2011) - [j8]Ana Bosque, Víctor Viñals
Filtering directory lookups in CMPs. Microprocess. Microsystems 35(8): 695-707 (2011) - [c25]Ana Bosque, Víctor Viñals
Filtering Directory Lookups in CMPs with Write-Through Caches. Euro-Par (1) 2011: 269-281 - 2010
- [c24]Ana Bosque, Víctor Viñals
Filtering Directory Lookups in CMPs. DSD 2010: 207-216 - [c23]Luis C. Aparicio, Juan Segarra
Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems. RTCSA 2010: 319-328
2000 – 2009
- 2009
- [j7]Enrique F. Torres, Pablo Ibáñez
Store Buffer Design for Multibanked Data Caches. IEEE Trans. Computers 58(10): 1307-1320 (2009) - [c22]Darío Suárez Gracia, Teresa Monreal, Fernando Vallejo, Ramón Beivide, Víctor Viñals:
Light NUCA: A proposal for bridging the inter-cache latency gap. DATE 2009: 530-535 - [c21]Benjamín Sahelices
A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors. Euro-Par 2009: 149-161 - 2008
- [c20]Luis M. Ramos, José Luis Briz
Low-Cost Adaptive Data Prefetching. Euro-Par 2008: 327-336 - [c19]Luis C. Aparicio, Juan Segarra
Avoiding the WCET Overestimation on LRU Instruction Cache. RTCSA 2008: 393-398 - [c18]Jesús Alastruey
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. SBAC-PAD 2008: 63-70 - 2007
- [j6]Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez
Data prefetching in a cache hierarchy with high bandwidth and capacity. SIGARCH Comput. Archit. News 35(4): 37-44 (2007) - [c17]Jesús Alastruey
Microarchitectural Support for Speculative Register Renaming. IPDPS 2007: 1-10 - [c16]Ana Bosque, Pablo Ibáñez
Characterization of Apache web server with Specweb2005. MEDEA@PACT 2007: 65-72 - [c15]Alicia Asín Pérez, Darío Suárez Gracia
A proposal to introduce power and energy notions in computer architecture laboratories. WCAE 2007: 52-57 - 2006
- [j5]Jesús Alastruey
Software Demand, Hardware Supply. IEEE Micro 26(4): 72-82 (2006) - [c14]Jesús Alastruey
Speculative early register release. Conf. Computing Frontiers 2006: 291-302 - [c13]Agustín De Dios Hernández, Benjamín Sahelices Fernández, Pablo Ibáñez
Speeding-Up Synchronizations in DSM Multiprocessors. Euro-Par 2006: 473-484 - [c12]Luis M. Ramos, José Luis Briz
Data prefetching in a cache hierarchy with high bandwidth and capacity. MEDEA@PACT 2006: 37-44 - 2005
- [j4]Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero:
Hardware support for early register release. Int. J. High Perform. Comput. Netw. 3(2/3): 83-94 (2005) - [j3]María Jesús Garzarán, Milos Prvulovic, José María Llabería
Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. ACM Trans. Archit. Code Optim. 2(3): 247-279 (2005) - [c11]Enrique F. Torres, Pablo Ibáñez
Store Buffer Design in First-Level Multibanked Data Caches. ISCA 2005: 469-480 - 2004
- [j2]Teresa Monreal
Late Allocation and Early Release of Physical Registers. IEEE Trans. Computers 53(10): 1244-1259 (2004) - [c10]Enrique F. Torres, Pablo Ibáñez
Contents Management in First-Level Multibanked Data Caches. Euro-Par 2004: 516-524 - 2003
- [c9]María Jesús Garzarán, Milos Prvulovic, Víctor Viñals
Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. IEEE PACT 2003: 170-181 - [c8]Enrique F. Torres, Pablo Ibáñez
Counteracting Bank Misprediction in Sliced First-Level Caches. Euro-Par 2003: 586-596 - [c7]María Jesús Garzarán, Milos Prvulovic, José María Llabería
Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. HPCA 2003: 191-202 - 2002
- [c6]Teresa Monreal
Hardware Schemes for Early Register Release. ICPP 2002: 5-13 - 2001
- [c5]María Jesús Garzarán, José Luis Briz, Pablo E. Ibáñez
Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware. PDP 2001: 345-354 - 2000
- [j1]Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals:
Dynamic Register Renaming Through Virtual-Physical Registers. J. Instr. Level Parallelism 2 (2000) - [c4]Luis M. Ramos, Pablo E. Ibáñez
Modeling load address behaviour through recurrences. ISPASS 2000: 101-108
1990 – 1999
- 1999
- [c3]Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
Delaying Physical Register Allocation through Virtual-Physical Registers. MICRO 1999: 186-192 - 1998
- [c2]Pablo Ibáñez
Characterization and Improvement of Load/Store Cache-based Prefetching. International Conference on Supercomputing 1998: 369-376 - 1996
- [c1]Pablo Ibáñez
Performance Assessment of Contents Management in Multilevel On-Chip Caches. EUROMICRO 1996: 431-440
Coauthor Index
Jesús Alastruey-Benedé
aka: Jesús Alastruey
aka: Jesús Alastruey
Teresa Monreal Arnal
aka: Teresa Monreal
aka: Teresa Monreal
José María Llabería
aka: José M. Llabería
aka: José M. Llabería
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