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Igor Lemberski
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2020 – today
- 2021
- [j6]Igor Lemberski
, Artjoms Suponenkovs
Resubstitution method for big size Boolean logic design targeting look-up-table implementation. Int. J. Circuit Theory Appl. 49(8): 2411-2424 (2021)
2010 – 2019
- 2019
- [c10]Igor Lemberski, Artjoms Suponenkovs, Marina Uhanova
LUT-Oriented Asynchronous Logic Design Based on Resubstitution. DTIS 2019: 1-4 - 2018
- [j5]Igor Lemberski, Artjoms Suponenkovs
Asynchronous logiс one-level LUT design based on partial acknowledgement. Microelectron. J. 80: 53-61 (2018) - [c9]Igor Lemberski, Artjoms Suponenkovs:
Asynchronous logic design targeting LUTs. MECO 2018: 1-6 - 2017
- [j4]Igor Lemberski:
Asynchronous Logic Implementation Based on Factorized DIMS. J. Circuits Syst. Comput. 26(5): 1750087:1-1750087:9 (2017) - 2015
- [j3]Igor Lemberski:
Literal Decomposition for LUT-Oriented Asynchronous Dual-Rail Logic Synthesis. J. Circuits Syst. Comput. 24(7): 1550110:1-1550110:11 (2015) - 2014
- [j2]Igor Lemberski, Petr Fiser
Asynchronous sum-of-products logic minimization and orthogonalization. Int. J. Circuit Theory Appl. 42(6): 562-571 (2014) - [j1]Igor Lemberski, Petr Fiser
Dual-rail asynchronous logic multi-level implementation. Integr. 47(1): 148-159 (2014) - 2010
- [c8]Igor Lemberski, Petr Fiser:
Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints. DSD 2010: 155-162
2000 – 2009
- 2009
- [c7]Igor Lemberski, Petr Fiser:
Asynchronous two-level logic of reduced cost. DDECS 2009: 68-73 - 2007
- [c6]Igor Lemberski:
Cost Effective Implementation of Asynchronous Two-Level Logic. World Congress on Engineering 2007: 159-164 - [c5]Igor Lemberski:
Avoiding Hazards for Speed-Independent Logic Design. World Congress on Engineering 2007: 274-278 - 2002
- [c4]Igor Lemberski, Mark B. Josephs
Optimal Two-Level Delay - Insensitive Implementation of Logic Functions. PATMOS 2002: 92-100
1990 – 1999
- 1999
- [c3]Igor Lemberski:
Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs. Great Lakes Symposium on VLSI 1999: 242-243 - 1998
- [c2]Igor Lemberski:
Modified Approach to Automata State Encoding for LUT FPGA Implementation. EUROMICRO 1998: 10196-10199 - [c1]Igor Lemberski, M. Ratniece:
XILINX4000 Architecture-Driven Synthesis for Speed. FPL 1998: 476-480
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