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17. FPGA 2009: Monterey, CA, USA
- Paul Chow, Peter Y. K. Cheung:
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009. ACM 2009, ISBN 978-1-60558-410-2 - Jason Helge Anderson:
Emerging application domains: research challenges and opportunities for FPGAs. 1-2
CAD tools 1
- Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour:
Towards automated ECOs in FPGAs. 3-12 - Qiang Wang, Subodh Gupta, Jason Helge Anderson:
Clock power reduction for virtex-5 FPGAs. 13-22 - Raphael Rubin, André DeHon:
Choose-your-own-adventure routing: lightweight load-time defect avoidance. 23-32
Architecture 1
- David M. Lewis, Elias Ahmed, David Cashman, Tim Vanderhoek, Christopher Lane, Andy Lee, Philip Pan:
Architectural enhancements in Stratix-IIITM and Stratix-IVTM. 33-42 - Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet:
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. 43-52 - Thomas C. P. Chau, Philip Heng Wai Leong
, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang:
A comparison of via-programmable gate array logic cell circuits. 53-62
High performance computing applications
- David B. Thomas, Lee W. Howes, Wayne Luk:
A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation. 63-72 - Daniel Le Ly, Paul Chow:
A high-performance FPGA architecture for restricted boltzmann machines. 73-82 - Edward C. Lin, Rob A. Rutenbar
A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer. 83-92
Novel applications
- Michael Haselman, Robert Miyaoka
FPGA-based front-end electronics for positron emission tomography. 93-102 - Junguk Cho, Shahnam Mirzaei
Fpga-based face detection system using Haar classifiers. 103-112 - Claudio Favi, Edoardo Charbon:
A 17ps time-to-digital converter implemented in 65nm FPGA technology. 113-120
Evening panel
- Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger:
CMOS vs Nano: comrades or rivals? 121-122
CAD tools 2
- David Sheldon, Frank Vahid:
Making good points: application-specific pareto-point generation for design space exploration using statistical methods. 123-132 - Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Jonathan Rose:
VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. 133-142 - Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox:
FPGA technology mapping with encoded libraries andstaged priority cuts. 143-150 - Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang:
Scalable don't-care-based logic optimization and resynthesis. 151-160
Architecture 2
- Chen Dong, Scott Chilstedt, Deming Chen:
FPCNA: a field programmable carbon nanotube array. 161-170 - Yee Jern Chong, Sri Parameswaran
Flexible multi-mode embedded floating-point unit for field programmable gate arrays. 171-180 - Alastair M. Smith, Steven J. E. Wilton, Joydip Das:
Wirelength modeling for homogeneous and heterogeneous FPGA architectural development. 181-190
High level synthesis
- Stephen Friedman, Allan Carroll, Brian Van Essen, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck:
SPR: an architecture-adaptive CGRA mapping tool. 191-200 - Jason Cong, Karthik Gururaj, Guoling Han:
Synthesis of reconfigurable high-performance multicore systems. 201-208 - Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang:
Intel® atomTM processor core made FPGA-synthesizable. 209-218
Network applications
- Weirong Jiang
Large-scale wire-speed packet classification on FPGAs. 219-228 - Viktor Pus, Jan Korenek:
Fast and scalable packet classification using perfect hash functions. 229-236
CAD tools 1
- Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton:
SmartOpt: an industrial strength framework for logic synthesis. 237-240 - Süleyman Sirri Demirsoy, Martin Langhammer:
Cholesky decomposition using fused datapath synthesis. 241-244 - Sumanta Chaudhuri
Diagonal tracks in FPGAs: a performance evaluation. 245-248
High performance computing applications
- Server Kasap
A high performance fpga-based implementation of position specific iterated blast. 249-252 - Dirk Koch, Christian Beckhoff, Jürgen Teich:
A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs. 253-256 - Johnny Tsung Lin Ho, Guy G. Lemieux:
PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions. 257-260 - Liu Ling, Neal Oliver, Bhushan Chitlur, Qigang Wang, Alvin Chen, Wenbo Shen, Zhihong Yu, Arthur Sheiman, Ian McCallum, Joseph Grecco, Henry Mitchel, Dong Liu, Prabhat Gupta:
High-performance, energy-efficient platforms using in-socket FPGA accelerators. 261-264
CAD tools 2
- Antonino Tumeo
HW/SW methodologies for synchronization in FPGA multiprocessors. 265-268 - Jeffrey M. Carver, Richard Neil Pittman, Alessandro Forin:
Automatic bus macro placement for partially reconfigurable FPGA designs. 269-272 - Ray Bittner:
Bus mastering PCI express in an FPGA. 273-276
Processors & CAD tools
- Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose:
Soft vector processors vs FPGA custom hardware: measuring and reducing the gap. 277 - Paul E. Marks, Cameron D. Patterson:
Data streaming and simd support for the microblaze architecture. 277 - Xinyu Li, Omar Hammami:
Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation. 278 - Timothy F. Beatty, Eric E. Aubanel, Kenneth B. Kent
Customizable bit-width in an OpenMP-based circuit design tool. 278 - Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Yi Zou, Zhiru Zhang, Sheng Zhou:
Revisiting bitwidth optimizations. 278 - Sayyed Arash Ostadzadeh
A clustering framework for task partitioning based on function-level data usage analysis. 279 - Akira Yamawaki, Masahiko Iwane:
An intermediate hardware model with load/store unit for C to FPGA. 279 - Zuo Wang, Feng Shi, Qi Zuo, Weixing Ji, Mengxiao Liu:
N-port memory mapping for LUT-based FPGAs. 279 - Cristinel Ababei:
Parallel placement for FPGAs revisited. 280
Applications
- Mohammed A. S. Abdallah, Omar S. Elkeelany, Ali T. Alouani:
Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controller. 281 - Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig:
Performance and power of cache-based reconfigurable computing. 281 - Melina Demertzi, Pedro C. Diniz, Mary W. Hall, Anna C. Gilbert, Yi Wang:
Computation reuse in domain-specific optimization of signal recognition. 281 - Like Yan, Gang Wang, Tianzhou Chen:
The input-aware dynamic adaptation of area and performance for reconfigurable accelerator. 281 - Florian Dittmann, Elmar Weber, Norma Montealegre:
Implementation of the reconfiguration port scheduling on the erlangen slot machine. 282 - Yanteng Sun, Peng Li
HMMer acceleration using systolic array based reconfigurable architecture. 282 - Seunghun Jin, Dongkyun Kim, Thien Cong Pham, Jae Wook Jeon:
FPGA implementation of real-time skin color detection with mean-based surface flattening. 283 - Gaurav Mittal, David Zaretsky, Prithviraj Banerjee:
Streaming implementation of a sequential decompression algorithm on an FPGA. 283 - Bowei Zhang, Guochang Gu, Lin Sun, Yanxia Wu:
32-bit floating-point FPGA gaussian elimination. 283-284
Architectures & applications
- Robin Pottathuparambil, Ron Sass:
A parallel/vectorized double-precision exponential core to accelerate computational science applications. 285 - Rosemary M. Francis, Simon W. Moore:
FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis. 285 - Lei Chen, Zhiquan Zhang, Zhiping Wen:
A novel BIST approach for testing input/output buffers in FPGAs. 285 - Abhranil Maiti, Patrick Schaumont
Impact and compensation of correlated process variation on ring oscillator based puf. 285 - JIanDe Yu, Jinmei Lai:
A novel minloop SB design to improve FPGA routability. 286 - Roto Le, Sherief Reda, R. Iris Bahar:
High-performance, cost-effective heterogeneous 3D FPGA architectures. 286 - Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau:
Measuring and modeling variabilityusing low-cost FPGAs. 286 - Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj:
3D configuration caching for 2D FPGAs. 286 - Michalis Vavouras, Kyprianos Papadimitriou, Ioannis Papaefstathiou:
Implementation of a genetic algorithm on a virtex-ii pro FPGA. 287 - Kanupriya Gulati, Sunil P. Khatri, Peng Li:
Closed-loop modeling of power and temperature profiles of FPGAs. 287
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