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Sam M. H. Ho
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2010 – 2019
- 2017
- [c8]Sam M. H. Ho, C.-H. Dominic Hung, Ho-Cheung Ng, Maolin Wang, Hayden Kwok-Hay So
:
A Parameterizable Activation Function Generator for FPGA-Based Neural Network Applications. FCCM 2017: 84 - [c7]Sam M. H. Ho, Hayden Kwok-Hay So
NnCore: A parameterized non-linear function generator for machine learning applications in FPGAs. FPT 2017: 160-167 - 2016
- [c6]Sam M. H. Ho, Maolin Wang, Ho-Cheung Ng, Hayden Kwok-Hay So
Towards FPGA-assisted spark: An SVM training acceleration case study. ReConFig 2016: 1-6 - [c5]Ho-Cheung Ng, Maolin Wang, Bob M. F. Chung, B. Sharat Chandra Varma
High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform. ReConFig 2016: 1-6 - 2010
- [c4]Steve C. L. Yuen, Yanqing Ai, Brian P. W. Chan, Thomas C. P. Chau, Sam M. H. Ho, Oscar K. L. Lau, Kong-Pang Pun, Philip Heng Wai Leong
Rapid prototyping on a structured ASIC fabric. ASP-DAC 2010: 379-380 - [c3]Thomas C. P. Chau, David W. L. Wu, Yanqing Ai, Brian P. W. Chan, Sam M. H. Ho, Oscar K. L. Lau, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Philip Heng Wai Leong
Design of a single layer programmable Structured ASIC library. DDECS 2010: 32-35 - [c2]Sam M. H. Ho, Steve C. L. Yuen, Hiu Ching Poon, Thomas C. P. Chau, Yanqing Ai, Philip Heng Wai Leong
Structured ASIC: Methodology and comparison. FPT 2010: 377-380
2000 – 2009
- 2009
- [c1]Thomas C. P. Chau, Philip Heng Wai Leong
A comparison of via-programmable gate array logic cell circuits. FPGA 2009: 53-62
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