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Peter Jamieson
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2020 – today
- 2024
- [j13]Ricardo S. Ferreira
, Michael Canesche
Examples and tutorials on using Google Colab and Gradio to create online interactive student-learning modules. Comput. Appl. Eng. Educ. 32(4) (2024) - [j12]Amin Sarihi, Ahmad Patooghy, Peter Jamieson, Abdel-Hameed A. Badawy:
Trojan playground: a reinforcement learning framework for hardware Trojan insertion and detection. J. Supercomput. 80(10): 14295-14329 (2024) - [c45]Amin Sarihi
TrojanForge: Generating Adversarial Hardware Trojan Examples Using Reinforcement Learning. MLCAD 2024: 21:1-21:7 - [i7]Amin Sarihi, Ahmad Patooghy, Abdel-Hameed A. Badawy, Peter Jamieson:
The Seeker's Dilemma: Realistic Formulation and Benchmarking for Hardware Trojan Detection. CoRR abs/2402.17918 (2024) - [i6]Amin Sarihi, Peter Jamieson, Ahmad Patooghy, Abdel-Hameed A. Badawy:
TrojanForge: Adversarial Hardware Trojan Examples with Reinforcement Learning. CoRR abs/2405.15184 (2024) - 2023
- [c44]Peter Jamieson, Suman Bhunia, Dhananjai M. Rao:
With ChatGPT, Do We have to Rewrite Our Learning Objectives - CASE Study in Cybersecurity. FIE 2023: 1-5 - [c43]Amin Sarihi, Peter Jamieson, Ahmad Patooghy, Abdel-Hameed A. Badawy:
Multi-Criteria Hardware Trojan Detection: A Reinforcement Learning Approach. MWSCAS 2023: 1093-1097 - [i5]Amin Sarihi, Peter Jamieson, Ahmad Patooghy, Abdel-Hameed A. Badawy:
Multi-criteria Hardware Trojan Detection: A Reinforcement Learning Approach. CoRR abs/2304.13232 (2023) - [i4]Amin Sarihi, Ahmad Patooghy, Peter Jamieson, Abdel-Hameed A. Badawy:
Trojan Playground: A Reinforcement Learning Framework for Hardware Trojan Insertion and Detection. CoRR abs/2305.09592 (2023) - [i3]Peter Jamieson, Suman Bhunia, Dhananjai M. Rao:
With ChatGPT, do we have to rewrite our learning objectives - CASE study in Cybersecurity. CoRR abs/2311.06261 (2023) - 2022
- [j11]Peter Jamieson
A Methodology for an FPGA Implementation of a Programmable Logic Controller to Control an Atomic Layer Deposition System. Int. J. Reconfigurable Comput. 2022: 8827417:1-8827417:10 (2022) - [c42]Amin Sarihi, Ahmad Patooghy, Peter Jamieson, Abdel-Hameed A. Badawy:
Hardware Trojan Insertion Using Reinforcement Learning. ACM Great Lakes Symposium on VLSI 2022: 139-142 - [i2]Amin Sarihi, Ahmad Patooghy, Peter Jamieson, Abdel-Hameed A. Badawy:
Hardware Trojan Insertion Using Reinforcement Learning. CoRR abs/2204.04350 (2022) - [i1]Peter Jamieson, Indrima Upadhyay:
A Technique to Create Weaker Abstract Board Game Agents via Reinforcement Learning. CoRR abs/2209.00711 (2022) - 2021
- [j10]Michael Canesche
TRAVERSAL: A Fast and Adaptive Graph-Based Placement and Routing for CGRAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1600-1612 (2021) - [j9]Michael Canesche, Westerley Carvalho, Lucas Reis, Matheus Aguilar de Oliveira, Salles V. G. Magalhães, Peter Jamieson, José Augusto Miranda Nacif, Ricardo Ferreira:
You Only Traverse Twice: A YOTT Placement, Routing, and Timing Approach for CGRAs. ACM Trans. Embed. Comput. Syst. 20(5s): 52:1-52:25 (2021) - [c41]Peter Jamieson, Santhiya Sampath Kumar, José Augusto Miranda Nacif, Ricardo S. Ferreira:
Analyzing a Low-bit rate Audio Codec - Codec2 - on an FPGA. CSCI 2021: 1486-1492 - [c40]Peter Jamieson, Ricardo S. Ferreira, José Augusto Miranda Nacif:
Personalizing Online Computer Engineering Resources and Labs for Digital, Embedded, and Computer System Courses. FIE 2021: 1-5 - [c39]Alejandro Cabrerizo, Will Zeurcher, Thomas Wright, Peter Jamieson
Lego®-like Bricks to Go from the Real to the Virtual World. HCI (44) 2021: 91-98 - [c38]Isaac Nelson, Ricardo S. Ferreira, José Augusto Miranda Nacif, Peter Jamieson:
Is It Time to Include High-Level Synthesis Design in Digital System Education for Undergraduate Computer Engineers? ISCAS 2021: 1-5 - 2020
- [c37]Peter Jamieson, Ricardo S. Ferreira, José Augusto Miranda Nacif:
GA-lapagos, an open-source c framework including a python-based system for data analysis. GECCO Companion 2020: 1589-1590 - [c36]Westerley Carvalho, Michael Canesche, Lucas Reis, Frank Sill Torres, Lucas B. da Silva, Peter Jamieson, José Augusto Miranda Nacif, Ricardo S. Ferreira:
A Design Exploration of Scalable Mesh-based Fully Pipelined Accelerators. FPT 2020: 233-236
2010 – 2019
- 2019
- [j8]Lucas Bragança da Silva, Ricardo S. Ferreira, Michael Canesche, Marcelo M. Menezes, Maria D. Vieira, Jeronimo Costa Penha
READY: A Fine-Grained Multithreading Overlay Framework for Modern CPU-FPGA Dataflow Applications. ACM Trans. Embed. Comput. Syst. 18(5s): 56:1-56:20 (2019) - 2018
- [c35]Alan Ehret, Peter Jamieson, Michel A. Kinsy:
Scalable Open-Source Reconfigurable Architecture for Bacterial Quorum Sensing Simulations. HEART 2018: 17:1-17:5 - [c34]Peter Jamieson, Ahmed Sanaullah, Martin C. Herbordt:
Benchmarking Heterogeneous HPC Systems Including Reconfigurable Fabrics: Community Aspirations for Ideal Comparisons. HPEC 2018: 1-6 - [c33]Fredy A. M. Alves, Peter Jamieson, Lucas Bragança
Lessons learned on which applications benefit when implemented on CPU-FPGA heterogeneous system. SAMOS 2018: 150-156 - 2017
- [c32]Peter Jamieson:
WIP - A modification to the case study method to teach students to read academic papers. FIE 2017: 1-4 - [c31]Fredy Augusto M. Alves, Peter Jamieson, Lucas B. da Silva, Ricardo S. Ferreira, José Augusto Miranda Nacif:
Designing a collision detection accelerator on a heterogeneous CPU-FPGA platform. ReConFig 2017: 1-6 - 2016
- [c30]Amber Franklin, Ryan Sunderhaus, Chris Bell, Peter Jamieson:
Improved method for creating criterion maps for automatic mind map analysis. FIE 2016: 1-6 - [c29]Peter Jamieson, Lindsay D. Grace
A framework to help analyze if creating a game to teach a learning objective is worth the work. FIE 2016: 1-7 - [c28]Peter Jamieson, Lindsay D. Grace
A simple multi-player video game framework for experimenting and teaching cultural understanding. MindTrek 2016: 422-425 - 2015
- [c27]Lindsay Grace
VerilogTown: cars, crashes and hardware design. Advances in Computer Entertainment 2015: 39:1-39:3 - [c26]Amber Franklin, Tuo Li, Peter Jamieson, Julie Semlak, Walter Vanderbush:
Evaluating metrics for automatic mind map assessment in various classes. FIE 2015: 1-8 - [c25]Peter Jamieson, Jeff Herdtner:
More missing the Boat - Arduino, Raspberry Pi, and small prototyping boards and engineering education needs them. FIE 2015: 1-6 - 2014
- [j7]Robert Collier, Christian Fobel, Ryan Pattison, Gary Gréwal, Shawki Areibi, Peter Jamieson:
Advancing genetic algorithm approaches to field programmable gate array placement with enhanced recombination operators. Evol. Intell. 7(4): 183-200 (2014) - [c24]Farnaz Gharibian, Lesley Shannon, Peter Jamieson:
A methodology for identifying and placing heterogeneous cluster groups based on placement proximity data (abstract only). FPGA 2014: 242 - [c23]Farnaz Gharibian, Lesley Shannon, Peter Jamieson:
Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data. FPL 2014: 1-6 - 2013
- [j6]Farnaz Gharibian, Lesley Shannon, Peter Jamieson, Kevin Chung:
Analyzing System-Level Information's Correlation to FPGA Placement. ACM Trans. Reconfigurable Technol. Syst. 6(3): 15:1-15:21 (2013) - [c22]Peter Jamieson, Farnaz Gharibian, Lesley Shannon:
Supergenes in a genetic algorithm for heterogeneous FPGA placement. IEEE Congress on Evolutionary Computation 2013: 253-260 - [c21]Peter Jamieson:
More graph comparison techniques on mind maps to provide students with feedback. FIE 2013: 992-998 - [c20]Peter Jamieson, Lindsay Grace
Metaheuristic Entry Points for Harnessing Human Computation in Mainstream Games. HCI (26) 2013: 156-163 - 2012
- [c19]Peter Jamieson:
Using modern graph analysis techniques on mind maps to help quantify learning. FIE 2012: 1-6 - [c18]Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent
The VTR project: architecture and CAD for FPGAs from verilog to routing. FPGA 2012: 77-86 - 2011
- [j5]Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Kenneth B. Kent
VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling. ACM Trans. Reconfigurable Technol. Syst. 4(4): 32:1-32:23 (2011) - [c17]Peter Jamieson:
Early project based learning improvements via a "star trek engineering room" game framework, and competition. FIE 2011: S4 - 2010
- [j4]Tobias Becker
Power Characterisation for Fine-Grain Reconfigurable Fabrics. Int. J. Reconfigurable Comput. 2010: 787405:1-787405:9 (2010) - [j3]Peter Jamieson, Tobias Becker
Benchmarking and evaluating reconfigurable architectures targeting the mobile domain. ACM Trans. Design Autom. Electr. Syst. 15(2): 14:1-14:24 (2010) - [j2]Peter A. Jamieson, Jonathan Rose:
Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1696-1709 (2010) - [c16]Peter Jamieson:
Persistent CAD for in-the-field Power Optimization. ERSA 2010: 267-270 - [c15]Peter Jamieson, Kenneth B. Kent
Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research. FCCM 2010: 149-156 - [c14]Peter Jamieson, Darrel Davis, Brooke Spangler:
The Mythical Creature Approach - A Simulation Alternative to Building Computer Architectures. FECS 2010: 23-28 - [c13]Peter A. Jamieson, Kenneth B. Kent:
Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only). FPGA 2010: 288 - [c12]Farnaz Gharibian, Lesley Shannon, Peter Jamieson:
Finding System-Level Information and Analyzing Its Correlation to FPGA Placement. FPL 2010: 544-549 - [c11]Peter Jamieson:
Revisiting Genetic Algorithms for the FPGA Placement Problem. GEM 2010: 16-22
2000 – 2009
- 2009
- [c10]Luke Terry, Vladimir Roitch, Shoeb Tufail, Kirit Singh, Omair Taraq, Wayne Luk, Peter Jamieson:
Harnessing Human Computation Cycles for the FPGA Placement Problem. ERSA 2009: 188-194 - [c9]Peter Jamieson, Tobias Becker
Benchmarking Reconfigurable Architectures in the Mobile Domain. FCCM 2009: 131-138 - [c8]Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Jonathan Rose:
VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. FPGA 2009: 133-142 - 2008
- [c7]Tobias Becker
Towards benchmarking energy efficiency of reconfigurable architectures. FPL 2008: 691-694 - 2007
- [c6]Peter Jamieson, Jonathan Rose:
Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow Clusters. FPT 2007: 57-64 - 2006
- [c5]Peter Jamieson, Jonathan Rose:
Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters. FPT 2006: 1-8 - 2005
- [c4]Peter Jamieson, Jonathan Rose:
A Verilog RTL Synthesis Tool for Heterogeneous FPGAs. FPL 2005: 305-310 - 2003
- [j1]Angelos Bilas, Courtney R. Gibson, Reza Azimi, Rosalia Christodoulopoulou, Peter Jamieson:
Using System Emulation to Model Next-Generation Shared Virtual Memory Clusters. Clust. Comput. 6(4): 325-338 (2003) - 2002
- [c3]Peter Jamieson, Angelos Bilas
CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory Clusters. HPCA 2002: 263-274 - 2001
- [c2]Peter Jamieson, Angelos Bilas
CableS : Thread Control and Memory System Extensions for Shared Virtual Memory Clusters. WOMPAT 2001: 170-184 - 2000
- [c1]Kathy Lynch, Angela Carbone, Peter Jamieson, David Arnott:
Adopting a studio-based education approach into information technology (poster session). ACSE 2000: 254
Coauthor Index
aka: José Augusto Miranda Nacif
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last updated on 2024-10-23 20:34 CEST by the dblp team
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