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Christian Pilato
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- affiliation: Politecnico di Milano, Italy
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2020 – today
- 2024
- [j26]Luca Collini
, Joey Ah-kiow
Using Static Analysis for Enhancing HLS Security. IEEE Embed. Syst. Lett. 16(2): 166-169 (2024) - [j25]Chao Lu
QHLS: An HLS Framework to Convert High-Level Descriptions to Quantum Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 3015-3026 (2024) - [c70]Christian Pilato, Subhadeep Banik, Jakub Beránek, Fabien Brocheton, Jerónimo Castrillón, Riccardo Cevasco, Radim Cmar, Serena Curzel, Fabrizio Ferrandi
A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach. DATE 2024: 1-6 - [c69]Stephanie Soldavini, Felix Suchert, Serena Curzel, Michele Fiorito, Karl F. A. Friebel, Fabrizio Ferrandi, Radim Cmar, Jerónimo Castrillón, Christian Pilato:
Etna: MLIR-Based System-Level Design and Optimization for Transparent Application Execution on CPU-FPGA Nodes. FCCM 2024: 224 - [i20]Ambra Di Paola, Serena Muraro, Roberto Marinelli, Christian Pilato:
Foundation Models in Augmentative and Alternative Communication: Opportunities and Challenges. CoRR abs/2401.08866 (2024) - [i19]Christian Pilato, Subhadeep Banik, Jakub Beránek, Fabien Brocheton, Jerónimo Castrillón, Riccardo Cevasco, Radim Cmar, Serena Curzel, Fabrizio Ferrandi
A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach. CoRR abs/2402.12612 (2024) - 2023
- [j24]Christian Pilato
Optimizing the Use of Behavioral Locking for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 462-472 (2023) - [j23]Raul Murillo
Generating Posit-Based Accelerators With High-Level Synthesis. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 4040-4052 (2023) - [j22]Stephanie Soldavini
Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics. ACM Trans. Reconfigurable Technol. Syst. 16(2): 21:1-21:34 (2023) - [j21]Mattia Tibaldi
A Survey of FPGA Optimization Methods for Data Center Energy Efficiency. IEEE Trans. Sustain. Comput. 8(3): 343-362 (2023) - [j20]Jitendra Bhandari
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction. IEEE Trans. Very Large Scale Integr. Syst. 31(10): 1459-1471 (2023) - [c68]Stephanie Soldavini, Donatella Sciuto, Christian Pilato:
Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization. ASP-DAC 2023: 172-177 - [c67]Chao Lu, Christian Pilato, Kanad Basu:
Towards High-Level Synthesis of Quantum Circuits. DATE 2023: 1-6 - [e2]Cristina Silvano
Embedded Computer Systems: Architectures, Modeling, and Simulation - 23rd International Conference, SAMOS 2023, Samos, Greece, July 2-6, 2023, Proceedings. Lecture Notes in Computer Science 14385, Springer 2023, ISBN 978-3-031-46076-0 [contents] - [i18]Mattia Tibaldi, Christian Pilato:
A Survey of FPGA Optimization Methods for Data Center Energy Efficiency. CoRR abs/2309.12884 (2023) - [i17]Stephanie Soldavini, Christian Pilato:
Platform-Aware FPGA System Architecture Generation based on MLIR. CoRR abs/2309.12917 (2023) - [i16]Christian Pilato, Francesca Palumbo:
CPS Workshop 2023 Proceedings. CoRR abs/2312.14578 (2023) - 2022
- [j19]Christian Pilato, Zhenman Fang, Yuko Hara-Azumi, Jim Hwang:
Introduction to the Special Section on High-level Synthesis for FPGA: Next-generation Technologies and Applications. ACM Trans. Design Autom. Electr. Syst. 27(4): 29:1-29:2 (2022) - [c66]Dominik Sisejkovic, Luca Collini
Designing ML-resilient locking at register-transfer level. DAC 2022: 769-774 - [c65]Chiara Muscari Tomajoli, Luca Collini
ALICE: an automatic design flow for eFPGA redaction. DAC 2022: 781-786 - [c64]Christian Pilato, Donatella Sciuto, Benjamin Tan, Siddharth Garg, Ramesh Karri
High-level design methods for hardware security: is it the right choice? invited. DAC 2022: 1375-1378 - [c63]Luca Collini
A Composable Design Space Exploration Framework to Optimize Behavioral Locking. DATE 2022: 1359-1364 - [c62]Luca Collini
Reconfigurable Logic for Hardware IP Protection: Opportunities and Challenges. ICCAD 2022: 131:1-131:7 - [c61]Gourav Takhar, Ramesh Karri
HOLL: Program Synthesis for Higher Order Logic Locking. TACAS (1) 2022: 3-24 - [p1]Christian Pilato, Donatella Sciuto, Francesco Regazzoni
Protecting Hardware IP Cores During High-Level Synthesis. Behavioral Synthesis for Hardware Security 2022: 95-115 - [e1]Raquel Lazcano López, Daniel Madroñal Quintín, Francesca Palumbo, Christian Pilato, Armando Tacchella:
Proceedings of the CPS Summer School PhD Workshop 2022 co-located with 4th Edition of the CPS Summer School (CPS 2022), Pula, Sardinia (Italy), September 19-23, 2022. CEUR Workshop Proceedings 3252, CEUR-WS.org 2022 [contents] - [i15]Gourav Takhar, Ramesh Karri, Christian Pilato, Subhajit Roy:
HOLL: Program Synthesis for Higher OrderLogic Locking. CoRR abs/2201.10531 (2022) - [i14]Dominik Sisejkovic
Designing ML-Resilient Locking at Register-Transfer Level. CoRR abs/2203.05399 (2022) - [i13]Stephanie Soldavini, Karl F. A. Friebel, Mattia Tibaldi, Gerald Hempel, Jerónimo Castrillón, Christian Pilato:
Automatic Creation of High-Bandwidth Memory Architectures from Domain-Specific Languages: The Case of Computational Fluid Dynamics. CoRR abs/2203.10850 (2022) - [i12]Chiara Muscari Tomajoli, Luca Collini
ALICE: An Automatic Design Flow for eFPGA Redaction. CoRR abs/2205.07425 (2022) - [i11]Stephanie Soldavini, Donatella Sciuto, Christian Pilato:
Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization. CoRR abs/2211.04361 (2022) - 2021
- [j18]Mattia Tibaldi
Automatic Generation of Heterogeneous SoC Architectures With Secure Communications. IEEE Embed. Syst. Lett. 13(2): 61-64 (2021) - [j17]Daniele Parravicini, Davide Conficconi
CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching. ACM Trans. Embed. Comput. Syst. 20(5s): 51:1-51:24 (2021) - [j16]Christian Pilato
ASSURE: RTL Locking Against an Untrusted Foundry. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1306-1318 (2021) - [c60]Karl F. A. Friebel
From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics. CLUSTER 2021: 759-766 - [c59]Nimisha Limaye, Animesh Basak Chowdhury, Christian Pilato, Mohammed Thari Nabeel, Ozgur Sinanoglu, Siddharth Garg, Ramesh Karri
Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks. DAC 2021: 91-96 - [c58]Fabrizio Ferrandi
Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications. DAC 2021: 1327-1330 - [c57]Hannah Badier, Christian Pilato, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat
Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis. DATE 2021: 52-55 - [c56]Christian Pilato, Stanislav Böhm, Fabien Brocheton, Jerónimo Castrillón, Riccardo Cevasco, Vojtech Cima, Radim Cmar, Dionysios Diamantopoulos, Fabrizio Ferrandi
EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms. DATE 2021: 1320-1325 - [c55]Shubham Rai
Vertical IP Protection of the Next-Generation Devices: Quo Vadis? DATE 2021: 1905-1914 - [c54]Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri
Exploring eFPGA-based Redaction for IP Protection. ICCAD 2021: 1-9 - [i10]Christian Pilato, Stanislav Böhm, Fabien Brocheton, Jerónimo Castrillón, Riccardo Cevasco, Vojtech Cima, Radim Cmar, Dionysios Diamantopoulos, Fabrizio Ferrandi, Jan Martinovic, Gianluca Palermo, Michele Paolino, Antonio Parodi, Lorenzo Pittaluga, Daniel Raho, Francesco Regazzoni, Katerina Slaninová, Christoph Hagleitner:
EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms. CoRR abs/2103.04185 (2021) - [i9]Christian Pilato, Francesco Regazzoni:
High-Level Synthesis of Security Properties via Software-Level Abstractions. CoRR abs/2104.01446 (2021) - [i8]Stephanie Soldavini, Christian Pilato:
Compiler Infrastructure for Specializing Domain-Specific Memory Templates. CoRR abs/2104.01448 (2021) - [i7]Christian Pilato, Luca Collini, Luca Cassano, Donatella Sciuto, Siddharth Garg, Ramesh Karri:
On the Optimization of Behavioral Logic Locking for High-Level Synthesis. CoRR abs/2105.09666 (2021) - [i6]Karl F. A. Friebel, Stephanie Soldavini, Gerald Hempel, Christian Pilato, Jerónimo Castrillón:
From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics. CoRR abs/2108.03326 (2021) - [i5]Stephanie Soldavini, Christian Pilato:
A Survey on Domain-Specific Memory Architectures. CoRR abs/2108.08672 (2021) - [i4]Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri:
Exploring eFPGA-based Redaction for IP Protection. CoRR abs/2110.13346 (2021) - [i3]Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri:
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction. CoRR abs/2111.04222 (2021) - 2020
- [c53]Chandan Karfa
Is Register Transfer Level Locking Secure? DATE 2020: 550-555 - [c52]Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni
Agile SoC Development with Open ESP : Invited Paper. ICCAD 2020: 96:1-96:9 - [i2]Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni:
Agile SoC Development with Open ESP. CoRR abs/2009.01178 (2020) - [i1]Christian Pilato, Animesh Basak Chowdhury, Donatella Sciuto, Siddharth Garg, Ramesh Karri:
ASSURE: RTL Locking Against an Untrusted Foundry. CoRR abs/2010.05344 (2020)
2010 – 2019
- 2019
- [j15]Christian Pilato
TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 798-808 (2019) - [j14]Kanad Basu, Samah Mohamed Saeed, Christian Pilato, Mohammed Ashraf, Mohammed Thari Nabeel, Krishnendu Chakrabarty
CAD-Base: An Attack Vector into the Electronics Supply Chain. ACM Trans. Design Autom. Electr. Syst. 24(4): 38:1-38:30 (2019) - [j13]Christian Pilato
Black-Hat High-Level Synthesis: Myth or Reality? IEEE Trans. Very Large Scale Integr. Syst. 27(4): 913-926 (2019) - [c51]Christian Pilato, Kanad Basu, Mohammed Shayan, Francesco Regazzoni
High-Level Synthesis of Benevolent Trojans. DATE 2019: 1124-1129 - 2018
- [j12]Pietro Fezzardi
Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis. IEEE Des. Test 35(5): 54-62 (2018) - [j11]Christian Pilato
Securing Hardware Accelerators: A New Challenge for High-Level Synthesis. IEEE Embed. Syst. Lett. 10(3): 77-80 (2018) - [j10]Catalin Bogdan Ciobanu
The Case for Polymorphic Registers in Dataflow Computing. Int. J. Parallel Program. 46(6): 1185-1219 (2018) - [c50]Christian Pilato, Luca P. Carloni:
DarkMem: Fine-grained power management of local memories for accelerators in embedded systems. ASP-DAC 2018: 696-701 - [c49]Christian Pilato, Francesco Regazzoni
TAO: techniques for algorithm-level obfuscation during high-level synthesis. DAC 2018: 155:1-155:6 - 2017
- [j9]Christian Pilato
System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(3): 435-448 (2017) - [c48]Christian Pilato:
Bridging the Gap Between Software and Hardware Designers Using High-Level Synthesis. PARCO 2017: 622-631 - 2016
- [j8]Marco Lattuada
Performance Estimation of Task Graphs Based on Path Profiling. Int. J. Parallel Program. 44(4): 735-771 (2016) - [j7]Razvan Nane
A Survey and Evaluation of FPGA High-Level Synthesis Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1591-1604 (2016) - [j6]Sara Vinco, Christian Pilato
Editorial: Special Issue on Innovative Design Methods for Smart Embedded Systems. ACM Trans. Embed. Comput. Syst. 15(2): 22e:1-22e:2 (2016) - [c47]Paolo Mantovani, Emilio G. Cota, Christian Pilato
Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip. CASES 2016: 3:1-3:10 - [c46]Christian Pilato
On the design of scalable and reusable accelerators for big data applications. Conf. Computing Frontiers 2016: 406-411 - [c45]Paolo Mantovani, Emilio G. Cota, Kevin Tien, Christian Pilato
An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems. DAC 2016: 157:1-157:6 - [c44]Gianluca C. Durelli, Fabrizio Spada, Christian Pilato
Scala-Based Domain-Specific Language for Creating Accelerator-Based SoCs. IPDPS Workshops 2016: 225-232 - 2015
- [j5]Dionisios N. Pnevmatikatos
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration. Microprocess. Microsystems 39(4-5): 321-338 (2015) - 2014
- [c43]Dionisios N. Pnevmatikatos
Effective Reconfigurable Design: The FASTER Approach. ARC 2014: 318-323 - [c42]Christian Pilato, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni:
System-level memory optimization for high-level synthesis of component-based SoCs. CODES+ISSS 2014: 18:1-18:10 - [c41]Giuseppe Di Guglielmo, Christian Pilato
A Design Methodology for Compositional High-Level Synthesis of Communication-Centric SoCs. DAC 2014: 128:1-128:6 - [c40]Gianluca Durelli, Fabrizio Spada, Riccardo Cattaneo
Adaptive Raytracing Implementation Using Partial Dynamic Reconfiguration. IPDPS Workshops 2014: 236-242 - [c39]Riccardo Cattaneo
PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures. IPDPS Workshops 2014: 243-250 - [c38]A. A. Nacci, Giovanni Bettinazzi, Christian Pilato
A SystemC-based framework for the simulation of appliances networks in energy-aware smart spaces. WF-IoT 2014: 485-490 - 2013
- [j4]Antonio Miele
A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs. Int. J. Embed. Real Time Commun. Syst. 4(1): 22-41 (2013) - [c37]Fabrizio Ferrandi
Ant Colony Optimization for mapping, scheduling and placing in reconfigurable systems. AHS 2013: 47-54 - [c36]Riccardo Cattaneo
Runtime adaptation on dataflow HPC platforms. AHS 2013: 84-91 - [c35]Christian Pilato
A2B: An integrated framework for designing heterogeneous and reconfigurable systems. AHS 2013: 198-205 - [c34]Christian Pilato
Bambu: A modular framework for the high level synthesis of memory-intensive applications. FPL 2013: 1-4 - [c33]Marco D. Santambrogio
The FASTER vision for designing dynamically reconfigurable systems. ICICDT 2013: 5-8 - [c32]Gianluca Durelli, Alessandro Antonio Nacci, Riccardo Cattaneo
A Flexible Interconnection Structure for Reconfigurable FPGA Dataflow Applications. IPDPS Workshops 2013: 192-201 - [c31]Fabio Cancare, Christian Pilato
D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems. ReCoSoC 2013: 1-6 - [c30]Riccardo Cattaneo
A framework for effective exploitation of partial reconfiguration in dataflow computing. ReCoSoC 2013: 1-8 - [c29]Riccardo Cattaneo
SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs. RSP 2013: 102-108 - [c28]Catalin Bogdan Ciobanu
Dataflow computing with Polymorphic Registers. ICSAMOS 2013: 314-321 - 2012
- [c27]Kyprianos Papadimitriou
Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration. CSE 2012: 391-398 - [c26]Andrea Cazzaniga, Gianluca Durelli, Christian Pilato
On the Development of a Runtime Reconfigurable Multicore System-on-Chip. DSD 2012: 132-135 - [c25]Dionisios N. Pnevmatikatos
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration. DSD 2012: 234-241 - [c24]Christian Pilato
On the automatic integration of hardware accelerators into FPGA-based embedded systems. FPL 2012: 607-610 - [c23]Alessandra Bonetto, Andrea Cazzaniga, Gianluca Durelli, Christian Pilato
An open-source design and validation platform for reconfigurable systems. FPL 2012: 707-710 - [c22]Antonio Miele
An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs. ISSoC 2012: 1-6 - [c21]Gianluca Durelli, Christian Pilato
Automatic run-time manager generation for reconfigurable MPSoC architectures. ReCoSoC 2012: 1-8 - [c20]Marco D. Santambrogio
Smart technologies for effective reconfiguration: The FASTER approach. ReCoSoC 2012: 1-7 - [c19]Alessandra Bonetto, Andrea Cazzaniga, Gianluca Durelli, Christian Pilato
TaBit: A framework for task graph to bitstream generation. ICSAMOS 2012: 201-208 - 2011
- [c18]Christian Pilato
A runtime adaptive controller for supporting hardware components with variable latency. AHS 2011: 153-160 - [c17]Martin Elhøj, André Inácio Reis, Renato P. Ribas, Fabrizio Ferrandi, Christian Pilato, Francesc Moll, Miguel Miranda, Petr Dobrovolný, Nigel Woolaway, Arnaud Grasset, Philippe Bonnot, Giuseppe Desoli, Davide Pandini:
SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels. ARCS Workshops 2011 - [c16]Christian Pilato, Fabrizio Ferrandi, Davide Pandini:
Evaluating Static CMOS Complex Cells in Technology Mapping. ARCS Workshops 2011 - [c15]Christian Pilato
A design methodology to implement memory accesses in high-level synthesis. CODES+ISSS 2011: 49-58 - [c14]Christian Pilato, Fabrizio Ferrandi
A design methodology for the automatic sizing of standard-cell libraries. ACM Great Lakes Symposium on VLSI 2011: 151-156 - [c13]Cristiana Bolchini
Combined architecture and hardening techniques exploration for reliable embedded system design. ACM Great Lakes Symposium on VLSI 2011: 301-306 - 2010
- [b1]Christian Pilato:
Design methodologies for improving embedded systems with hardware accelerators. Polytechnic University of Milan, Italy, 2010 - [j3]Koen Bertels, Vlad Mihai Sima
HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms. IEEE Micro 30(5): 88-97 (2010) - [j2]Fabrizio Ferrandi
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(6): 911-924 (2010) - [c12]Fabrizio Ferrandi
Mapping and scheduling of parallel C applications with ant colony optimization onto heterogeneous reconfigurable MPSoCs. ASP-DAC 2010: 799-804 - [c11]Christian Pilato
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells. ISVLSI 2010: 23-28
2000 – 2009
- 2009
- [c10]Antonino Tumeo
Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach. CODES+ISSS 2009: 443-452 - [c9]Antonino Tumeo
HW/SW methodologies for synchronization in FPGA multiprocessors. FPGA 2009: 265-268 - [c8]Marco Branca, Lorenzo Camerini, Fabrizio Ferrandi
Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems. GECCO 2009: 1435-1442 - [c7]Marco Lattuada
Performance modeling of parallel applications on MPSoCs. SoC 2009: 64-67 - [c6]Fabrizio Ferrandi
Performance estimation for task graphs combining sequential path profiling and control dependence regions. MEMOCODE 2009: 131-140 - 2008
- [j1]Christian Pilato
Improving evolutionary exploration to area-time optimization of FPGA designs. J. Syst. Archit. 54(11): 1046-1057 (2008) - [c5]Christian Pilato
High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis. IEEE Congress on Evolutionary Computation 2008: 3334-3341 - [c4]Fabrizio Ferrandi
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis. ISVLSI 2008: 417-422 - [c3]Antonino Tumeo
Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems. ICSAMOS 2008: 142-149 - 2007
- [c2]Christian Pilato
Fitness inheritance in evolutionary and multi-objective high-level synthesis. IEEE Congress on Evolutionary Computation 2007: 3459-3466 - [c1]Fabrizio Ferrandi
An Evolutionary Approach to Area-Time Optimization of FPGA designs. ICSAMOS 2007: 145-152
Coauthor Index
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