research-article

Towards automated ECOs in FPGAs

Authors:

Andrew C. Ling,

Stephen D. Brown,

Sean SafarpourAuthors Info & Claims

FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

Pages 3 - 12

https://doi.org/10.1145/1508128.1508131

Published: 22 February 2009 Publication History

Abstract

During the FPGA design flow, engineering change orders (ECOs) have become an essential methodology to apply late-stage specification changes and bug fixes. ECOs are beneficial since they are applied directly to a place-and-routed netlist which preserves most of the engineering effort invested previously. Unfortunately, designers often apply ECOs in a manual fashion which has an unpredictable impact on the design's final correctness and end costs. As a solution, we introduce an automated method to tackle the ECO problem. Specifically, we introduce a resynthesis technique which can automatically update the functionality of a circuit by leveraging the existing logic within the design; thereby removing the inefficient manual effort required by a designer. Our technique is robust enough to handle a wide range of changes. Furthermore, our technique can successfully make late-stage functional changes while minimally perturbing the place-and-routed netlist: something that is necessary for ECOs. When applied to several benchmarks on Altera's Stratix architecture, we show that our approach can automatically apply ECOs in over 80% of the cases presented. Furthermore, our technique does this with a minimal impact to the circuit performance where on average over 90% of the placement and routing wires remain unchanged.

References

[1]

K. Morris, "Time for a change: Mentor mondernizes the ECO," FPGA and Structured ASIC, May 2006.

[2]

S. Golson, "The human ECO compiler," Trilobyte Systems, 2004.

[3]

R. Goering, "Post-silicon debugging worth a second look, EEtimes," 2007. {Online}. Available: http://www.eetimes.com/

[4]

D. Platzker, "FPGA design meets the heisenberg uncertainty principle," SOCcentral, 2005.

[5]

Altera Corporation, Quartus II University Interface Program. {Online}. Available: http://www.altera.com/education/univ/research/unvquip.html

[6]

J. Cong and M. Sarrafzadeh, "Incremental physical design, in International Symposium on Physical Design," 2000, pp. 84--93.

Digital Library

[7]

J. C. Madre, O. Coudert, and J. P. Billon, "Automating the diagnosis and the rectification of digital errors with PRIAM," in International Conference on Computer-Aided Design, 1989, pp. 30--33.

[8]

K. Chang, I. L. Markov, and V. Bertacco, "Fixing design errors with counterexamples and resynthesis," IEEE Journal on Technology in Computer-Aided Design, vol. 27, no. 1, pp. 184--188, 2008.

Digital Library

[9]

Y.-S. Yang, S. Sinha, A. Veneris, and R. K. Brayton, "Automating logic rectification by approximate SPFDs," in Asia-South Pacific Design Automation Conference, 2007, pp. 402--407.

Digital Library

[10]

S.-Y. Huang, K.-C. Chen, and K.-T. Cheng, "AutoFix: a hybrid tool for automatic logic rectification," vol. 18, no. 9, pp. 1376--1384, Sept. 1999.

Digital Library

[11]

Mentor Graphics, "Precision synthesis: product overview, Advanced FPGA Design Synthesis," 2005.

[12]

Xilinx Corporation, "SmartCompile technology: SmartGuide," Xilinx Press Release, 2008.

[13]

M. W. Moskewicz, C. F. Madigan, Y. Zhao, L. Zhang, and S. Malik, "Chaff: Engineering an Efficient SAT Solver," in Proceedings of the 38th Design Automation Conference (Design Automation Conference'01), 2001. {Online}. Available: citeseer.ist.psu.edu/moskewicz01chaff.html

Digital Library

[14]

T. Larrabee, "Test pattern generation using Boolean satisfiability," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 1, pp. 4--15, Jan. 1992.

Digital Library

[15]

S. Safarpour, H. Mangassarian, A. G. Veneris, M. H. Liffiton, and K. A. Sakallah, "Improved design debugging using maximum satisfiability," in Formal Methods in Computer-Aided Design, 2007, pp. 13--19.

Digital Library

[16]

C.-C. Lee, J.-H. R. Jiang, C.-Y. R. Huang, and A. Mishchenko, "Scalable exploration of functional dependency by interpolation and incremental SAT solving," in International Conference on Computer-Aided Design, 2007, pp. 227--233.

Digital Library

[17]

K. L. McMillan, "Interpolation and SAT-based model checking," vol. 2725, pp. 1--13, 2008.

[18]

V. Manohararajah, D. P. Singh, and S. D. Brown, "Post-placement BDD-based decomposition for FPGAs," in Field-Programmable Logic, Aug. 2005, pp. 31--38.

Cited By

Xue YYang C(2017)Path reuse-aware routing for non-volatile memory based FPGAsIntegration10.1016/j.vlsi.2016.10.00558(505-517)Online publication date: Jun-2017
https://doi.org/10.1016/j.vlsi.2016.10.005
Xue YCronin PYang CHu J(2015)Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs2015 25th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2015.7294013(1-8)Online publication date: Sep-2015
https://doi.org/10.1109/FPL.2015.7294013
Ren HPuri RReddy LKrishnaswamy SWashburn CEarl JKeinert JMacii E(2013)Intuitive ECO synthesis for high performance circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485529(1002-1007)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485529
Show More Cited By

Index Terms

Towards automated ECOs in FPGAs
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis

Recommendations

Toward Automated ECOs in FPGAs

Engineering change orders (ECOs), which are used to apply late-stage specification changes and bug fixes, have become an important part of the field-programmable gate array design flow. ECOs are beneficial since they are applied directly to a placed-and-...
An efficient and effective analytical placer for FPGAs
DAC '13: Proceedings of the 50th Annual Design Automation Conference

The increasing design complexity of modern circuits has made traditional FPGA placement techniques not efficient anymore. To improve the scalability, commercial FPGA placement tools have started migrating to analytical placement. In this paper, we ...
Routing-architecture-aware analytical placement for heterogeneous FPGAs
DAC '15: Proceedings of the 52nd Annual Design Automation Conference

Placement is a crucial stage for FPGA implementation. Most FPGA placers optimize their placement results by minimizing half-perimeter wirelength (HPWL). Due to the segmented routing architecture in FPGAs, however, the HPWL function cannot model routed ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

February 2009

302 pages

ISBN:9781605584102

DOI:10.1145/1508128

General Chair:
Paul Chow
University of Toronto, Canada
,
Program Chair:
Peter Cheung
Imperial College London, UK

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 February 2009

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

FPGA '09

Sponsor:

FPGA '09: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 22 - 24, 2009

California, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

16
Total Citations
View Citations
315
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 05 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Xue YYang C(2017)Path reuse-aware routing for non-volatile memory based FPGAsIntegration10.1016/j.vlsi.2016.10.00558(505-517)Online publication date: Jun-2017
https://doi.org/10.1016/j.vlsi.2016.10.005
Xue YCronin PYang CHu J(2015)Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs2015 25th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2015.7294013(1-8)Online publication date: Sep-2015
https://doi.org/10.1109/FPL.2015.7294013
Ren HPuri RReddy LKrishnaswamy SWashburn CEarl JKeinert JMacii E(2013)Intuitive ECO synthesis for high performance circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485529(1002-1007)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485529
Tang KHuang PChou CHuang CRosenstiel WMacii E(2012)Multi-patch generation for multi-error logic rectification by interpolation with cofactor reductionProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2493091(1567-1572)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2493091
Kai-Fu Tang Po-Kai Huang Chun-Nan Chou Chung-Yang Huang (2012)Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.1109/DATE.2012.6176722(1567-1572)Online publication date: Mar-2012
https://doi.org/10.1109/DATE.2012.6176722
Huang SLin WHuang CPhillips JHu AGraeb H(2011)Match and replaceProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132421(383-388)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132421
Tang KWu CHuang PHuang CStok LDutt NHassoun S(2011)Interpolation-based incremental ECO synthesis for multi-error logic rectificationProceedings of the 48th Design Automation Conference10.1145/2024724.2024758(146-151)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024758
Chen DSingh DWawrzynek JCompton K(2011)Line-level incremental resynthesis techniques for FPGAsProceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1950413.1950442(133-142)Online publication date: 27-Feb-2011
https://dl.acm.org/doi/10.1145/1950413.1950442
Shi XZeng DHu YLin GZaiane O(2011)Enhancement of incremental design for FPGAs using circuit similarity2011 12th International Symposium on Quality Electronic Design10.1109/ISQED.2011.5770732(1-8)Online publication date: Mar-2011
https://doi.org/10.1109/ISQED.2011.5770732
Huang SLin W(Ric) Huang C(2011)Match and replace -- A functional ECO engine for multi-error circuit rectificationProceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2011.6105358(383-388)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.1109/ICCAD.2011.6105358
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten