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Ray Bittner
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2020 – today
- 2020
- [c13]Bita Darvish Rouhani, Daniel Lo, Ritchie Zhao, Ming Liu, Jeremy Fowers, Kalin Ovtcharov, Anna Vinogradsky, Sarah Massengill, Lita Yang, Ray Bittner, Alessandro Forin, Haishan Zhu, Taesik Na, Prerak Patel, Shuai Che, Lok Chand Koppaka, Xia Song, Subhojit Som, Kaustav Das, Saurabh Tiwary, Steven K. Reinhardt, Sitaram Lanka, Eric S. Chung, Doug Burger:
Pushing the Limits of Narrow Precision Inferencing at Cloud Scale with Microsoft Floating Point. NeurIPS 2020
2010 – 2019
- 2014
- [j1]Ray Bittner, Erik Ruf, Alessandro Forin:
Direct GPU/FPGA communication Via PCI express. Clust. Comput. 17(2): 339-348 (2014) - 2012
- [c12]Jason Oberg, Ken Eguro, Ray Bittner, Alessandro Forin:
Random decision tree body part recognition using FPGAs. FPL 2012: 330-337 - [c11]Ray Bittner:
Speedy bus mastering PCI express. FPL 2012: 523-526 - [c10]Ray Bittner, Erik Ruf:
Direct GPU/FPGA Communication via PCI Express. ICPP Workshops 2012: 135-139 - 2011
- [c9]Mahsan Rofouei, Mike Sinclair, Ray Bittner, Tom Blank, Nick Saw, Gerald DeJean, Jeff Heffron:
A Non-invasive Wearable Neck-Cuff System for Real-Time Sleep Monitoring. BSN 2011: 156-161 - [c8]Ji Sun, Ray Bittner, Ken Eguro:
FPGA side-channel receivers. FPGA 2011: 267-276
2000 – 2009
- 2009
- [c7]Turner Whitted, James T. Kajiya, Erik Ruf, Ray Bittner:
Embedded function composition. High Performance Graphics 2009: 47-50 - [c6]Ray Bittner:
The Speedy DDR2 Controller For FPGAs. ERSA 2009: 205-211 - [c5]Ray Bittner:
Bus mastering PCI express in an FPGA. FPGA 2009: 273-276 - [c4]Ray Bittner, Mike Sinclair:
VersaPatch: A Low Cost 2.5D Capacitive Touch Sensor. HCI (2) 2009: 407-416 - 2006
- [c3]Lin Zhong, Mike Sinclair, Ray Bittner:
A Phone-Centered Body Sensor Network Platform: Cost, Energy Efficiency & User Interface. BSN 2006: 179-182
1990 – 1999
- 1997
- [b1]Ray Bittner:
Wormhole Run-Time Reconfiguration: Conceptualization and VLSI Design of a High Performance Computing System. Virginia Tech, Blacksburg, VA, USA, 1997 - [c2]Ray Bittner, Peter M. Athanas:
Computing kernels implemented with a wormhole RTR CCM. FCCM 1997: 98-105 - [c1]Ray Bittner, Peter M. Athanas:
Wormhole Run-Time Reconfiguration. FPGA 1997: 79-85
Coauthor Index
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last updated on 2024-04-25 05:48 CEST by the dblp team
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