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2020 – today
- 2024
- [c98]Bardia Babaei
, Dirk Koch
Analysis of Process Variation Within Clock Regions of AMD-Xilinx UltraScale+ Devices. ARC 2024: 193-209 - [c97]Riadh Ben Abdelhamid, Vladislav Válek, Dirk Koch:
SPARKLE: A 1,024-Core/16,384-Thread Single FPGA Many-Core RISC-V Barrel Processor Overlay. ASAP 2024: 118-119 - [c96]Bardia Babaei, Dirk Koch:
Ph.D. Project: ManAge: A Tool for Timing Characterization of FPGAs. FCCM 2024: 239-240 - 2023
- [c95]Shaden M. Alismail
Memory-Aware Scheduling for a Resource-Elastic FPGA Operating System. ARC 2023: 81-96 - [c94]Shaden M. Alismail, Dirk Koch:
Efficient Resource Scheduling for Runtime Reconfigurable Systems on FPGAs. FPL 2023: 123-129 - [c93]Myrtle Shah, Jakob Ternes, Dirk Koch:
FABulous Demo: Open Source FPGA on Sky130. FPL 2023: 365 - 2022
- [j13]Christophe Bobda
The Future of FPGA Acceleration in Datacenters and the Cloud. ACM Trans. Reconfigurable Technol. Syst. 15(3): 34:1-34:42 (2022) - [c92]King Lok Chung
How to Shrink My FPGAs - Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA Fabrics. FPGA 2022: 13-23 - [c91]Bardia Babaei
Tunable Fine-grained Clock Phase-shifting for FPGAs. FPL 2022: 384-390 - [c90]Bardia Babaei, Dirk Koch:
Precise Characterizing of FPGAs in Production Systems. FPL 2022: 464-465 - [c89]Kaspar Mätas, Kristiyan Manev, Joseph Powell, Dirk Koch:
FPL Demo: Runtime Stream Processing with Resource-Elastic Pipelines on FPGAs. FPL 2022: 466 - [c88]Joseph Powell, Kaspar Matas, Kristiyan Manev, Dirk Koch:
FPL Demo: FPGA Bitstream Virus Scanning. FPL 2022: 469 - [c87]Kristiyan Manev, Joseph Powell
byteman: A Bitstream Manipulation Framework. FPT 2022: 1-9 - [c86]Kaspar Mätas
Automated Generation and Orchestration of Stream Processing Pipelines on FPGAs. FPT 2022: 1-10 - 2021
- [j12]Tuan La
Denial-of-Service on FPGA-based Cloud Infrastructures - Attack and Defense. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(3): 441-464 (2021) - [j11]Frank Hannig, Dirk Koch:
Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors. J. Signal Process. Syst. 93(12): 1363-1364 (2021) - [c85]Nguyen Cong Dao, Dirk Koch:
Memristor-based Pass Gate Targeting FPGA Look-Up Table. ICEIC 2021: 1-4 - [c84]Shaza Zeitouni, Jo Vliegen, Tommaso Frassetto, Dirk Koch, Ahmad-Reza Sadeghi, Nele Mentens
Trusted Configuration in Cloud FPGAs. FCCM 2021: 233-241 - [c83]Dirk Koch, Nguyen Dao, Bea Healy, Jing Yu, Andrew Attwood:
FABulous: An Embedded FPGA Framework. FPGA 2021: 45-56 - [c82]Jing Yu, Andrew Attwood, Nguyen Dao, Dirk Koch:
The FABulous Open eFPGA Ecosystem in Action - From Specifications to Chips to Running Bitsteams. FPL 2021: 406 - [c81]Nguyen Cong Dao, Dirk Koch:
Memristor-Based Pass Gate for FPGA Programmable Routing Switch. ISCAS 2021: 1-5 - 2020
- [j10]Tuan Minh La
FPGADefender: Malicious Self-oscillator Scanning for Xilinx UltraScale + FPGAs. ACM Trans. Reconfigurable Technol. Syst. 13(3): 15:1-15:31 (2020) - [j9]Anuj Vaishnav
FOS: A Modular FPGA Operating System for Dynamic Workloads. ACM Trans. Reconfigurable Technol. Syst. 13(4): 20:1-20:28 (2020) - [j8]Charalampos Kritikakis, Dirk Koch:
Enabling Dynamic System Integration on Maxeler HLS Platforms. J. Signal Process. Syst. 92(9): 887-905 (2020) - [c80]Dirk Koch, Frank Hannig, Javier Navaridas:
Message from the Conference Chairs - ASAP 2020. ASAP 2020: i-ii - [c79]Kaspar Matas
Power-hammering through Glitch Amplification - Attacks and Mitigation. FCCM 2020: 65-69 - [c78]Kaspar Matas
Invited Tutorial: FPGA Hardware Security for Datacenters and Beyond. FPGA 2020: 11-20 - [c77]Tuan La, Kaspar Matas
Securing FPGA Accelerators at the Electrical Level for Multi-tenant Platforms. FPL 2020: 361-362 - [c76]Kristiyan Manev, Dirk Koch:
Resource Elastic Database Acceleration. FPL 2020: 363-364 - [c75]Kaspar Mätas
Transparent Integration of a Dynamic FPGA Database Acceleration System. FPL 2020: 365-366 - [c74]Khoa Dang Pham, Anuj Vaishnav, Joseph Powell, Dirk Koch:
A Self-Compilation Flow Demo on FOS - The FPGA Operating System. FPL 2020: 368 - [c73]Tuan La, Kaspar Matas
Demo: A Closer Look at Malicious Bitstreams. FPL 2020: 369 - [c72]Nguyen Dao, Andrew Attwood, Bea Healy, Dirk Koch:
FlexBex: A RISC-V with a Reconfigurable Instruction Extension. FPT 2020: 190-195 - [c71]Khoa Dang Pham, Dirk Koch, Anuj Vaishnav, Konstantinos Georgopoulos, Pavlos Malakonakis, Aggelos Ioannou
Moving Compute towards Data in Heterogeneous multi-FPGA Clusters using Partial Reconfiguration and I/O Virtualisation. FPT 2020: 221-226 - [i6]Anuj Vaishnav, Khoa Dang Pham, Joseph Powell, Dirk Koch:
FOS: A Modular FPGA Operating System for Dynamic Workloads. CoRR abs/2001.09990 (2020)
2010 – 2019
- 2019
- [c70]Charalampos Kritikakis, Dirk Koch:
End-to-end Dynamic Stream Processing on Maxeler HLS Platforms. ASAP 2019: 59-66 - [c69]Khoa Dang Pham, Malte Vesper, Dirk Koch, Eddie Hung:
EFCAD - An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-Compilation. FCCM 2019: 5-8 - [c68]Anuj Vaishnav, Khoa Dang Pham, Kristiyan Manev, Dirk Koch:
The FOS (FPGA Operating System) Demo. FPL 2019: 429 - [c67]Anuj Vaishnav
Heterogeneous Resource-Elastic Scheduling for CPU+FPGA Architectures. HEART 2019: 1:1-1:6 - [c66]Kristiyan Manev, Anuj Vaishnav
Scalable Filtering Modules for Database Acceleration on FPGAs. HEART 2019: 4:1-4:6 - [c65]Kristiyan Manev, Anuj Vaishnav, Dirk Koch:
Unexpected Diversity: Quantitative Memory Analysis for Zynq UltraScale+ Systems. FPT 2019: 179-187 - 2018
- [c64]Nicolae Bogdan Grigore, Charalampos Kritikakis, Dirk Koch:
HLS Enabled Partially Reconfigurable Module Implementation. ARCS 2018: 269-282 - [c63]Jose Raul Garcia Ordaz
A Soft Dual-Processor System with a Partially Run-Time Reconfigurable Shared 128-Bit SIMD Engine. ASAP 2018: 1-8 - [c62]Anuj Vaishnav
Resource Elastic Virtualization for FPGAs Using OpenCL. FPL 2018: 111-118 - [c61]Anuj Vaishnav
A Survey on FPGA Virtualization. FPL 2018: 131-138 - [c60]Anuj Vaishnav
Live Migration for OpenCL FPGA Accelerators. FPT 2018: 38-45 - [c59]Kristiyan Manev, Dirk Koch:
Large Utility Sorting on FPGAs. FPT 2018: 334-337 - [c58]Khoa Dang Pham, Edson L. Horta, Dirk Koch, Anuj Vaishnav
IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs. MCSoC 2018: 36-43 - [e3]Mladen Berekovic, Rainer Buchty, Heiko Hamann, Dirk Koch, Thilo Pionteck:
Architecture of Computing Systems - ARCS 2018 - 31st International Conference, Braunschweig, Germany, April 9-12, 2018, Proceedings. Lecture Notes in Computer Science 10793, Springer 2018, ISBN 978-3-319-77609-5 [contents] - 2017
- [c57]Khoa Dang Pham, Edson L. Horta, Dirk Koch:
BITMAN: A tool and API for FPGA bitstream manipulations. DATE 2017: 894-897 - [c56]Gengting Liu, Jim D. Garside
Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation. FPL 2017: 1-8 - [c55]Jose Raul Garcia Ordaz
Making a case for an ARM Cortex-A9 CPU interlay replacing the NEON SIMD unit. FPL 2017: 1-4 - [c54]Anuj Vaishnav
A security library for FPGA interlays. FPL 2017: 1-4 - [c53]Jose Raul Garcia Ordaz
HLS Compilation for CPU Interlays. HEART 2017: 27:1-27:6 - 2016
- [c52]Jose Raul Garcia Ordaz
soft-NEON: A study on replacing the NEON engine of an ARM SoC with a reconfigurable fabric. ASAP 2016: 229-230 - [c51]Iakovos Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Dimitrios S. Nikolopoulos, Dirk Koch, John Goodacre, Ioannis Sourdis, Vassilis Papaefstathiou, Marcello Coppola
ECOSCALE: Reconfigurable computing and runtime system for future exascale systems. DATE 2016: 696-701 - [c50]Wei Song
Parallel Hardware Merge Sorter. FCCM 2016: 95-102 - [c49]Malte Vesper, Dirk Koch, Kizheppatt Vipin
JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication. FPL 2016: 1-9 - [c48]Zhenzhong Xiao, Dirk Koch, Mikel Luján:
A partial reconfiguration controller for Altera Stratix V FPGAs. FPL 2016: 1-4 - [p4]Dirk Koch, Daniel Ziener
FPGA Versus Software Programming: Why, When, and How? FPGAs for Software Programmers 2016: 1-21 - [e2]Dirk Koch, Frank Hannig
FPGAs for Software Programmers. Springer 2016, ISBN 978-3-319-26406-6 [contents] - 2015
- [j7]Jo Vliegen, Nele Mentens
Practical feasibility evaluation and improvement of a pay-per-use licensing scheme for hardware IP cores in Xilinx FPGAs. J. Cryptogr. Eng. 5(2): 113-122 (2015) - [c47]Michael Xi Yue, Dirk Koch, Guy G. F. Lemieux:
Rapid Overlay Builder for Xilinx FPGAs. FCCM 2015: 17-20 - [c46]Nicolae Bogdan Grigore, Dirk Koch:
Placing partially reconfigurable stream processing applications on FPGAs. FPL 2015: 1-4 - [i5]Frank Hannig
Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015). CoRR abs/1508.06320 (2015) - 2014
- [j6]Christian Beckhoff, Dirk Koch, Jim Tørresen:
Design Tools for Implementing Self-Aware and Fault-Tolerant Systems on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 7(2): 14:1-14:23 (2014) - [c45]Christian Beckhoff, Dirk Koch, Jim Tørresen:
Portable module relocation and bitstream compression for Xilinx FPGAs. FPL 2014: 1-8 - [c44]Dirk Koch, Christian Beckhoff:
Hierarchical reconfiguration of FPGAs. FPL 2014: 1-8 - [i4]Frank Hannig, Dirk Koch, Daniel Ziener:
Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014). CoRR abs/1408.4423 (2014) - 2013
- [b2]Dirk Koch:
Partial Reconfiguration on FPGAs - Architectures, Tools and Applications. Lecture Notes in Electrical Engineering 153, Springer 2013, ISBN 978-1-4614-1224-3, pp. 1-252 - [c43]Christian Beckhoff, Dirk Koch, Jim Tørresen:
Automatic Floorplanning and Interface Synthesis of Island Style Reconfigurable Systems with GoAhead. ARCS 2013: 303-316 - [c42]Christian Beckhoff, Alexander Wold, Anders Fritzell, Dirk Koch, Jim Tørresen:
Building partial systems with GoAhead. FPL 2013: 1 - [c41]Dirk Koch, Christian Beckhoff, Guy G. F. Lemieux:
An efficient FPGA overlay for portable custom instruction set extensions. FPL 2013: 1-8 - [c40]Jochen Vandorpe, Jo Vliegen, Ruben Smeets, Nele Mentens, Milos Drutarovský, Michal Varchola, Kerstin Lemke-Rust, Paul Plöger, Peter Samarin, Dirk Koch, Yngve Hafting, Jim Tørresen:
Remote FPGA design through eDiViDe - European Digital Virtual Design Lab. FPL 2013: 1 - [c39]Dirk Koch, Christian Beckhoff, Alexander Wold, Jim Tørresen:
EasyPR - An easy usable open-source PR system. FPT 2013: 414-417 - [c38]Alexander Wold, Dirk Koch, Jim Tørresen:
Thermal Aware Module Placement for Heterogeneous 3D-IC Based FPGAs. IPDPS Workshops 2013: 281-286 - [c37]Simen Gimle Hansen, Dirk Koch, Jim Tørresen:
Simulation framework for cycle-accurate RTL modeling of partial run-time reconfiguration in VHDL. ReCoSoC 2013: 1-8 - [c36]Alexander Wold, Dirk Koch, Jim Tørresen:
Component based design using constraint programming for module placement on FPGAs. ReCoSoC 2013: 1-8 - 2012
- [j5]Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich:
Dynamic Defragmentation of Reconfigurable Devices. ACM Trans. Reconfigurable Technol. Syst. 5(2): 8:1-8:20 (2012) - [c35]Dirk Koch, Jim Tørresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, Jürgen Teich, Michael Feilen, Walter Stechele:
Partial Reconfiguration on FPGAs in Practice - Tools and Applications. ARCS Workshops 2012: 297-319 - [c34]Alexander Wold, Dirk Koch, Jim Tørresen:
Design techniques for increasing performance and resource utilization of reconfigurable soft CPUs. DDECS 2012: 50-55 - [c33]Christian Beckhoff, Dirk Koch, Jim Tørresen:
Go Ahead: A Partial Reconfiguration Framework. FCCM 2012: 37-44 - [e1]Dirk Koch, Satnam Singh, Jim Tørresen:
22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012. IEEE 2012, ISBN 978-1-4673-2257-7 [contents] - 2011
- [j4]Kazi Shah Nawaz Ripon, Kyrre Glette, Dirk Koch, Mats Høvin, Jim Tørresen:
Genetic algorithm using a modified backward pass heuristic for the dynamic facility layout problem. Paladyn J. Behav. Robotics 2(3): 164-174 (2011) - [c32]Dirk Koch, Jim Tørresen:
FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting. FPGA 2011: 45-54 - [c31]Dirk Koch, Jim Tørresen:
A Routing Architecture for Mapping Dataflow Graphs at Run-Time. FPL 2011: 286-290 - [c30]Simen Gimle Hansen, Dirk Koch, Jim Tørresen:
High Speed Partial Run-Time Reconfiguration Using Enhanced ICAP Hard Macro. IPDPS Workshops 2011: 174-180 - [c29]Christian Beckhoff, Dirk Koch, Jim Tørresen:
Migrating Static Systems to Partially Reconfigurable Systems on Spartan-6 FPGAs. IPDPS Workshops 2011: 212-219 - [c28]Alexander Wold, Dirk Koch, Jim Tørresen:
Enhancing Resource Utilization with Design Alternatives in Runtime Reconfigurable Systems. IPDPS Workshops 2011: 264-270 - [c27]Christian Beckhoff, Dirk Koch, Jim Tørresen:
The Xilinx Design Language (XDL): Tutorial and use cases. ReCoSoC 2011: 1-8 - 2010
- [c26]Dirk Koch, Christian Beckhoff, Jim Tørresen:
Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs. FCCM 2010: 69-72 - [c25]Andreas Oetken, Stefan Wildermann, Jürgen Teich, Dirk Koch:
A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs. FPL 2010: 234-239 - [c24]Christian Beckhoff, Dirk Koch, Jim Tørresen:
Short-Circuits on FPGAs Caused by Partial Runtime Reconfiguration. FPL 2010: 596-601 - [c23]Dirk Koch, Christian Beckhoff, Jim Tørresen:
Obstacle-free two-dimensional online-routing for run-time reconfigurable FPGA-based systems. FPT 2010: 208-215 - [c22]Dirk Koch, Christian Beckhoff, Jim Tørresen:
Advanced partial run-time reconfiguration on Spartan-6 FPGAs. FPT 2010: 361-364 - [c21]Dirk Koch, Jim Tørresen:
Routing optimizations for component-based system design and partial run-time reconfiguration on FPGAs. FPT 2010: 460-464 - [c20]Dirk Koch, Christian Beckhoff, Jim Tørresen:
Zero logic overhead integration of partially reconfigurable modules. SBCCI 2010: 103-108 - [p3]Ali Ahmadinia, Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Dirk Koch, Mateusz Majer, Nils Schweer, Jürgen Teich, Christopher Tessars, Jan van der Veen:
ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices. Dynamically Reconfigurable Systems 2010: 199-221 - [p2]Christian Haubelt
ReCoNets - Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections. Dynamically Reconfigurable Systems 2010: 223-243 - [i3]Dirk Koch:
Advances in Component-based System Design and Partial Run-time Reconfiguration. Dynamically Reconfigurable Architectures 2010 - [i2]Jim Tørresen, Dirk Koch:
A new project to address run-time reconfigurable hardware systems. Dynamically Reconfigurable Architectures 2010 - [i1]Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich:
No-Break Dynamic Defragmentation of Reconfigurable. CoRR abs/1012.5330 (2010)
2000 – 2009
- 2009
- [b1]Dirk Koch:
Architectures, methods, and tools for distributed run-time reconfigurable FPGA-based systems. University of Erlangen-Nuremberg, 2009, pp. 1-289 - [j3]Dirk Koch, Christian Beckhoff, Jürgen Teich:
Hardware Decompression Techniques for FPGA-Based Embedded Systems. ACM Trans. Reconfigurable Technol. Syst. 2(2): 9:1-9:23 (2009) - [c19]Dirk Koch, Christian Beckhoff, Jürgen Teich:
Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems. FCCM 2009: 251-254 - [c18]Dirk Koch, Christian Beckhoff, Jürgen Teich:
A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs. FPGA 2009: 253-256 - 2008
- [j2]Martin Rump
Photo-realistic Rendering of Metallic Car Paint from Image-Based Measurements. Comput. Graph. Forum 27(2): 527-536 (2008) - [c17]Robert Brendle, Thilo Streichert, Dirk Koch, Christian Haubelt
Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks. ARCS 2008: 117-129 - [c16]Dirk Koch, Christian Haubelt
Efficient Reconfigurable On-Chip Buses for FPGAs. FCCM 2008: 287-290 - [c15]Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich:
No-break dynamic defragmentation of reconfigurable devices. FPL 2008: 113-118 - [c14]Dirk Koch, Christian Beckhoff, Jürgen Teich:
ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS. FPL 2008: 119-124 - [p1]Thilo Streichert, Christian Haubelt
Concepts for Self-Adaptive and Self-Healing Networked Embedded Systems. Organic Computing 2008: 241-260 - 2007
- [c13]Dirk Koch, Christian Haubelt
Efficient hardware checkpointing: concepts, overhead analysis, and implementation. FPGA 2007: 188-196 - [c12]Dirk Koch, Christian Beckhoff, Jürgen Teich:
Bitstream Decompression for High Speed FPGA Configuration from Slow Memories. FPT 2007: 161-168 - [c11]Dirk Koch, Christian Haubelt, Thilo Streichert, Jürgen Teich:
Modeling and Synthesis of Hardware-Software Morphing. ISCAS 2007: 2746-2749 - 2006
- [j1]Thilo Streichert, Dirk Koch, Christian Haubelt
Modeling and Design of Fault-Tolerant and Self-Adaptive Reconfigurable Networked Embedded Systems. EURASIP J. Embed. Syst. 2006 (2006) - [c10]Dirk Koch, Thilo Streichert, Steffen Dittrich, Christian Strengert, Christian Haubelt
An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks. ARCS 2006: 202-216 - [c9]Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich:
A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES 2006: 189-195 - [c8]Dirk Koch, Matthiaas Koerber, Jürgen Teich:
Searching RC5-Keys with Distributed Reconfigurable Computing. ERSA 2006: 42-48 - 2004
- [c7]Dirk Koch, Jürgen Teich:
Platform-independent methodology for partial reconfiguration. Conf. Computing Frontiers 2004: 398-403 - [c6]Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich:
A Dynamic NoC Approach for Communication in Reconfigurable Devices. FPL 2004: 1032-1036 - [c5]Dirk Koch:
Preemptive Hardware Task Management. FPL 2004: 1174 - [c4]Dirk Koch, Ali Ahmadinia, Christophe Bobda, Heiko Kalte:
FPGA architecture extensions for preemptive multitasking and hardware defragmentation. FPT 2004: 433-436 - [c3]Christian Haubelt, Dirk Koch, Jürgen Teich:
Basic OS Support for Distributed Reconfigurable Hardware. SAMOS 2004: 30-38 - [c2]Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich:
Task scheduling for heterogeneous reconfigurable computers. SBCCI 2004: 22-27 - 2003
- [c1]Christian Haubelt
ReCoNet: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware. SBCCI 2003: 343-348
Coauthor Index
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