poster

Streaming implementation of a sequential decompression algorithm on an FPGA

Authors:

David C. Zaretsky,

Prithviraj BanerjeeAuthors Info & Claims

FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

Page 283

https://doi.org/10.1145/1508128.1508195

Published: 22 February 2009 Publication History

Abstract

This paper describes an FPGA based implementation of a real time compression algorithm used in transactions between financial institutions such as exchanges and trading houses. FIX is a protocol that has gained widespread popularity for exchanging financial information such as stock prices and purchases over the Internet. If a financial trader can speed up the processing of these protocols, he can make significant financial profits by buying or selling stocks when there is a lot of variability in the share prices. Our methodology tries to recognize and exploit streaming characteristics of the software design in order to implement a pipelined parallel processing system in reconfigurable hardware. It introduces the concept of caches to keep stream pipelines filled more often. The system implemented on a Xilinx Virtex5 LX110T FPGA shows a 17x speedup in throughput over a software implementation running on a dual core Intel Pentium workstation. These techniques are being developed as part of commercial compiler project to automatically translate software binaries to streaming RTL VHDL systems.

References

[1]

FAST Specification 1.x.1, 2006-12-20, FAST ProtocolSM, FIX Protocol Ltd, http://www.fixprotocol.org.

[2]

Field Encoding Specification, 1.0, 2006-1-11, FAST ProtocolSM, FIX Protocol Ltd, http://www.fixprotocol.org.

[3]

FIX 5.0 Specification, FIX Protocol Ltd, http://www.fixprotocol.org.

[4]

M. Wolfe, "High performance compilers for parallel computing," Addison-Wesley Publishing, 1996, 260--277

Digital Library

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M.A. Franklin, E.J. Tyson, J. Buckley, P. Crowley, J. Maschmeyer, "Auto-pipe and the X language: a pipeline design tool and description language," in Parallel and Distributed Processing Symposium, 2006. IPDPS 2006.

Digital Library

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M.B. Gokhale, J.M. Stone, J. Arnold, and M. Kalinowski, "Stream-Oriented FPGA Computing in the Streams-C High Level Language," in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 2000.

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N. Bellas, S.M. Chai, M. Dwyer, D. Linzmeier, "FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators," in Proc. 20th IEEE International Parallel & Distributed Processing Symposium, 2006.

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R.D. Chamberlain and M.A. Franklin, "Automatic Deployment of Streaming Applications on Hybrid Architectures," in Proc. of 11th High Performance Embedded Computing Workshop, September 2007.

[9]

R.D. Chamberlain, J.M. Lancaster, and R.K. Cytron, "Visions for Application Development on Hybrid Computing Systems," Parallel Computing, May 2008.

Digital Library

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S. Ciricescu, R. Essick, B. Lucas, P. May, K. Moat, et al. "The reconfigurable streaming vector processor (RSVPTM)," in Proc. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003, pp. 141--150

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S.M. Chai, N. Bellas, M. Dwyer and D. Linzmeier, "Stream Memory Subsystem in Reconfigurable Platforms," in 2nd Workshop on Architecture Research using FPGA Platforms, 2006.

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U. Kapasi, W. Dally, S. Rixner, J. Owens, and B. Khailany, "The Imagine stream processor," in Proc. International Conference on Computer Design, 2002, pp. 282--288

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W. Dally, F. Labonte, A. Das, P. Hanrahan, A. Jung-Ho, et al. "Merrimac: supercomputing with streams," in ACM/IEEE Conference of Supercomputing, 2003, pp. 35--42

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W. Thies, M. Karczmarek, and S. Amarasinghe, "StreamIt: A compiler for streaming applications," MIT-LCS Technical Memo LCS-TM-622, Cambridge, MA, 2001.

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Xilinx PCI Express Endpoint Block Plus v1.5 datasheet DS551. Xilinx, Inc. http://www.xilinx.com

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Xilinx Virtex-5 Embedded Tri-Mode Ethernet MAC wrapper v1.3 datasheet DS550, Xilinx, Inc. http://www.xilinx.com

Cited By

Litz HLeber CGeib BSmelyanskiy MDixon MDaly DEleftheriou MMoreira JRyu K(2011)DSL programmable engine for high frequency trading accelerationProceedings of the fourth workshop on High performance computational finance10.1145/2088256.2088268(31-38)Online publication date: 13-Nov-2011
https://dl.acm.org/doi/10.1145/2088256.2088268
Leber CGeib BLitz H(2011)High Frequency Trading Acceleration Using FPGAsProceedings of the 2011 21st International Conference on Field Programmable Logic and Applications10.1109/FPL.2011.64(317-322)Online publication date: 5-Sep-2011
https://dl.acm.org/doi/10.1109/FPL.2011.64

Index Terms

Streaming implementation of a sequential decompression algorithm on an FPGA
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems

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Information

Published In

cover image ACM Conferences

FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

February 2009

302 pages

ISBN:9781605584102

DOI:10.1145/1508128

General Chair:
Paul Chow
University of Toronto, Canada
,
Program Chair:
Peter Cheung
Imperial College London, UK

Copyright © 2009 Copyright is held by the author/owner(s).

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 February 2009

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FPGA '09: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 22 - 24, 2009

California, Monterey, USA

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Cited By

Litz HLeber CGeib BSmelyanskiy MDixon MDaly DEleftheriou MMoreira JRyu K(2011)DSL programmable engine for high frequency trading accelerationProceedings of the fourth workshop on High performance computational finance10.1145/2088256.2088268(31-38)Online publication date: 13-Nov-2011
https://dl.acm.org/doi/10.1145/2088256.2088268
Leber CGeib BLitz H(2011)High Frequency Trading Acceleration Using FPGAsProceedings of the 2011 21st International Conference on Field Programmable Logic and Applications10.1109/FPL.2011.64(317-322)Online publication date: 5-Sep-2011
https://dl.acm.org/doi/10.1109/FPL.2011.64

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