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Greg Yeric
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- affiliation: ARM Inc., Austin, TX, USA
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2020 – today
- 2022
- [j10]Kyungwook Chang
, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 410-423 (2022) - [c20]Saurabh V. Suryavanshi, Greg Yeric, Max Irby, X. M. Henry Huang, Glen Rosendale, Lucian Shifren:
Extreme Temperature (> 200 °C), Radiation Hard (> 1 Mrad), Dense (sub-50 nm CD), Fast (2 ns write pulses), Non-Volatile Memory Technology. IMW 2022: 1-4 - 2021
- [i3]Chi-Shuen Lee, Brian Cline, Saurabh Sinha, Greg Yeric, H.-S. Philip Wong:
Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor. CoRR abs/2109.07915 (2021) - 2020
- [i2]Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava, Shidhartha Das, Brian Cline, Greg Yeric:
Stack up your chips: Betting on 3D integration to augment Moore's Law scaling. CoRR abs/2005.10866 (2020)
2010 – 2019
- 2019
- [j9]Kyungwook Chang
System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 888-898 (2019) - [c19]Greg Yeric:
IC Design After Moore's Law. CICC 2019: 1-150 - 2018
- [i1]Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric:
Standard Cell Library Design and Optimization Methodology for ASAP7 PDK. CoRR abs/1807.11396 (2018) - 2017
- [j8]Kyungwook Chang
Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 2118-2129 (2017) - [c18]Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric:
Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper). ICCAD 2017: 999-1004 - [c17]Jiaojiao Ou, Xiaoqing Xu, Brian Cline, Greg Yeric, David Z. Pan:
DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node. ICCD 2017: 403-410 - [c16]Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Frequency and time domain analysis of power delivery network for monolithic 3D ICs. ISLPED 2017: 1-6 - 2016
- [j7]Robert C. Aitken, Vikas Chandra, Brian Cline, Shidhartha Das, David Pietromonaco, Lucian Shifren, Saurabh Sinha, Greg Yeric:
Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches. IET Comput. Digit. Tech. 10(6): 315-322 (2016) - [j6]Lawrence T. Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, Greg Yeric:
ASAP7: A 7-nm finFET predictive process design kit. Microelectron. J. 53: 105-115 (2016) - [c15]Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Match-making for monolithic 3D IC: finding the right technology node. DAC 2016: 77:1-77:6 - [c14]Greg Yeric:
At the core of system scaling. ESSCIRC 2016: 1-2 - [c13]Kyungwook Chang, Saurabh Sinha, Brian Cline, Raney Southerland, Michael Doherty, Greg Yeric, Sung Kyu Lim
Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools. ICCAD 2016: 130 - [c12]Kwang Min Kim, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study. ISLPED 2016: 70-75 - [c11]Kartik Acharya, Kyungwook Chang, Bon Woong Ku, Shreepad Panth, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Monolithic 3D IC design: Power, performance, and area impact at 7nm. ISQED 2016: 41-48 - 2015
- [j5]Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan:
Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 699-712 (2015) - [c10]Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
Power benefit study of monolithic 3D IC at the 7nm technology node. ISLPED 2015: 201-206 - [c9]Saurabh Sinha, Lucian Shifren, Vikas Chandra, Brian Cline, Greg Yeric, Robert C. Aitken, Bingjie Cheng, Andrew R. Brown, Craig Riddet, C. Alexandar, Campbell Millar, Asen Asenov:
Circuit design perspectives for Ge FinFET at 10nm and beyond. ISQED 2015: 57-60 - 2014
- [c8]Robert C. Aitken, Greg Yeric, Brian Cline, Saurabh Sinha, Lucian Shifren, Imran Iqbal, Vikas Chandra:
Physical design and FinFETs. ISPD 2014: 65-68 - [c7]Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan:
Self-aligned double patterning aware pin access and standard cell layout co-optimization. ISPD 2014: 101-108 - [c6]Greg Yeric:
Design, technology and yield in the post-moore era. ITC 2014: 1 - 2013
- [c5]Greg Yeric, Brian Cline, Saurabh Sinha, David Pietromonaco, Vikas Chandra, Rob Aitken:
The past present and future of design-technology co-optimization. CICC 2013: 1-8 - 2012
- [c4]Saurabh Sinha
Exploring sub-20nm FinFET design with predictive technology models. DAC 2012: 283-288 - [c3]Saurabh Sinha, Brian Cline, Greg Yeric, Vikas Chandra, Yu Cao
Design benchmarking to 7nm with FinFET predictive technology models. ISLPED 2012: 15-20 - 2011
- [c2]Rob Aitken, Greg Yeric, David Flynn:
Correlating models and silicon for improved parametric yield. DATE 2011: 1159-1163
2000 – 2009
- 2007
- [c1]Srikanth Venkataraman, Ruchir Puri, Steve Griffith, Ankush Oberai, Robert Madge, Greg Yeric, Walter Ng, Yervant Zorian:
Making Manufacturing Work For You. DAC 2007: 107-108 - 2005
- [j4]Greg Yeric, Ethan Cohen, John Garcia, Kurt Davis, Esam Salem, Gary Green:
Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below. IEEE Des. Test Comput. 22(3): 232-239 (2005)
1990 – 1999
- 1993
- [j3]Victor Martin Agostinelli Jr., Gregory Munson Yeric, A. F. Tasch Jr.:
Universal MOSFET hole mobility degradation models for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(3): 439-445 (1993) - [j2]C. Patrick Yue, Victor Martin Agostinelli Jr., Gregory Munson Yeric, A. F. Tasch Jr.:
Improved universal MOSFET electron mobility degradation models for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(10): 1542-1546 (1993) - 1990
- [j1]Gregory Munson Yeric, A. F. Tasch Jr., Sanjay K. Banerjee:
A universal MOSFET mobility degradation model for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(10): 1123-1126 (1990)
Coauthor Index
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