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Physical design and FinFETs

Authors:

Vikas ChandraAuthors Info & Claims

ISPD '14: Proceedings of the 2014 on International symposium on physical design

Pages 65 - 68

https://doi.org/10.1145/2560519.2565871

Published: 30 March 2014 Publication History

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Abstract

FinFETs have recently overtaken bulk CMOS transistors as the device of choice for systems-on-chip. This paper provides some background on FinFETs together with their associated manufacturing processes and shows how they influence physical design of standard cells as well as place & route and timing closure for larger blocks.

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Cited By

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Li YLin YMadhusudan MSharma ASapatnekar SHarjani RHu J(2022)Performance-driven Wire Sizing for Analog Integrated CircuitsACM Transactions on Design Automation of Electronic Systems10.1145/355954228:2(1-23)Online publication date: 24-Dec-2022
https://dl.acm.org/doi/10.1145/3559542
Li YLin SNishizawa SSu HFong MChen OOnodera H(2022)NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid MapIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.316733941:12(5568-5581)Online publication date: Dec-2022
https://doi.org/10.1109/TCAD.2022.3167339
Salimath VSechen C(2020)Optimal Standard Cell Library Composition for 7nm2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9180595(1-5)Online publication date: Oct-2020
https://doi.org/10.1109/ISCAS45731.2020.9180595
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Index Terms

Physical design and FinFETs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Emerging technologies

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Information & Contributors

Information

Published In

ISPD '14: Proceedings of the 2014 on International symposium on physical design

March 2014

180 pages

ISBN:9781450325929

DOI:10.1145/2560519

General Chair:
Cliff Sze
IBM Research
,
Program Chair:
Azadeh Davoodi
University of Wisconsin - Madison

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 March 2014

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Keynote

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ISPD'14

Sponsor:

SIGDA

ISPD'14: International Symposium on Physical Design

March 30 - April 2, 2014

California, Petaluma, USA

Acceptance Rates

ISPD '14 Paper Acceptance Rate 14 of 40 submissions, 35%;

Overall Acceptance Rate 62 of 172 submissions, 36%

Upcoming Conference

ISPD '25

Sponsor:
sigda

International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

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Cited By

View all

Li YLin YMadhusudan MSharma ASapatnekar SHarjani RHu J(2022)Performance-driven Wire Sizing for Analog Integrated CircuitsACM Transactions on Design Automation of Electronic Systems10.1145/355954228:2(1-23)Online publication date: 24-Dec-2022
https://dl.acm.org/doi/10.1145/3559542
Li YLin SNishizawa SSu HFong MChen OOnodera H(2022)NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid MapIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.316733941:12(5568-5581)Online publication date: Dec-2022
https://doi.org/10.1109/TCAD.2022.3167339
Salimath VSechen C(2020)Optimal Standard Cell Library Composition for 7nm2020 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS45731.2020.9180595(1-5)Online publication date: Oct-2020
https://doi.org/10.1109/ISCAS45731.2020.9180595
Rostami Sani SFatima Khan FRazzaq AYe A(2020)Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology2020 30th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL50879.2020.00043(214-219)Online publication date: Aug-2020
https://doi.org/10.1109/FPL50879.2020.00043
Vashishtha VClark L(2019)A FinFET-Based Framework for VLSI Design at the 7 nm NodeEnergy Efficient Computing & Electronics10.1201/9781315200705-1(3-49)Online publication date: 31-Jan-2019
https://doi.org/10.1201/9781315200705-1
van Santen VAmrouch HHenkel J(2019)Modeling and Evaluating the Gate Length Dependence of BTIIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2018.288585066:9(1527-1531)Online publication date: Sep-2019
https://doi.org/10.1109/TCSII.2018.2885850
S SHolla RRaghu R(2019)Low Power Physical Design and Verification in 16nm FinFET Technology2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA)10.1109/ICECA.2019.8822211(936-940)Online publication date: Jun-2019
https://doi.org/10.1109/ICECA.2019.8822211
Guo XStan MGuo XStan M(2019)Design and Aging Challenges in FinFET Circuits and Internet of Things (IoT) ApplicationsCircadian Rhythms for Future Resilient Electronic Systems10.1007/978-3-030-20051-0_6(143-189)Online publication date: 13-Jun-2019
https://doi.org/10.1007/978-3-030-20051-0_6
Vashishtha VWalia S(2018)ASAP7: A finFET-Based Framework for Academic VLSI Design at the 7 nm NodeLow Power Semiconductor Devices and Processes for Emerging Applications in Communications, Computing, and Sensing10.1201/9780429503634-1(1-44)Online publication date: 6-Aug-2018
https://doi.org/10.1201/9780429503634-1
Kang IPark DHan CCheng CHu S(2018)Fast and precise routability analysis with conditional design rulesProceedings of the 20th System Level Interconnect Prediction Workshop10.1145/3225209.3225210(1-8)Online publication date: 23-Jun-2018
https://dl.acm.org/doi/10.1145/3225209.3225210
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