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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 28
Volume 28, Number 1, January 2009
- Radu Marculescu
, Ümit Y. Ogras
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives. 3-21 - Paolo Maffezzoni, Dario D'Amore:
Evaluating Pulling Effects in Oscillators Due to Small-Signal Injection. 22-31 - Ender Yilmaz, Günhan Dündar
Analog Layout Generator for CMOS Circuits. 32-45 - Jing Li
Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications. 46-59 - María C. Molina, Rafael Ruiz-Sautua, Pedro Garcia-Repetto, Román Hermida
Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications. 60-73 - Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes:
Signature-Based SER Analysis and Design of Logic Circuits. 74-86 - Jung Hwan Choi, Nilanjan Banerjee, Kaushik Roy:
Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters. 87-97 - Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang
An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs. 98-110 - Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs. 111-120 - Irith Pomeranz, Sudhakar M. Reddy:
Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions. 121-129 - Lerong Cheng, Jinjun Xiong
Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting. 130-140 - Zhuo Feng, Peng Li, Yaping Zhan:
An On-the-Fly Parameter Dimension Reduction Approach to Fast Second-Order Statistical Static Timing Analysis. 141-153 - Gianpiero Cabodi, Sergio Nocco, Stefano Quer
Strengthening Model Checking Techniques With Inductive Invariants. 154-158 - Hoseok Chang, Wonyong Sung:
Access-Pattern-Aware On-Chip Memory Allocation for SIMD Processors. 158-163
Volume 28, Number 2, February 2009
- Cheng-Hong Li, Luca P. Carloni
Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip. 165-178 - Kristofer Vorwerk, Andrew A. Kennings, Jonathan W. Greene:
Improving Simulated Annealing-Based FPGA Placement With Directed Moves. 179-192 - Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang
A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control. 193-206 - Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong:
Substrate Topological Routing for High-Density Packages. 207-216 - Huaizhi Wu, Martin D. F. Wong
Incremental Improvement of Voltage Assignment. 217-230 - Cristian Soviani, Ilija Hadzic, Stephen A. Edwards:
Synthesis and Optimization of Pipelined Packet Processors. 231-244 - Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Timing-Aware Multiple-Delay-Fault Diagnosis. 245-258 - Zhanglei Wang, Hongxia Fang, Krishnendu Chakrabarty
Deviation-Based LFSR Reseeding for Test-Data Compression. 259-271 - Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou:
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging. 272-284 - Ho Fai Ko, Nicola Nicolici:
Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug. 285-297 - Sobeeh Almukhaizim, Ozgur Sinanoglu
Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test. 298-302
Volume 28, Number 3, March 2009
- Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework. 305-315 - Dipanjan Sengupta, Resve A. Saleh:
Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip Design. 316-326 - Youngsoo Shin, Seungwhun Paik, Hyung-Ock Kim:
Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements. 327-339 - Muhammet Mustafa Ozdal:
Detailed-Routing Algorithms for Dense Pin Clusters in Integrated Circuits. 340-349 - Hushrav Mogal, Haifeng Qian
Fast and Accurate Statistical Criticality Computation Under Process Variations. 350-363 - Alessandro Pinto
A Methodology for Constraint-Driven Synthesis of On-Chip Communications. 364-377 - Martino Ruggiero, Davide Bertozzi, Luca Benini
Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms. 378-391 - Mihir R. Choudhury, Kartik Mohanram:
Reliability Analysis of Logic Circuits. 392-405 - S. Saqib Khursheed, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod:
Diagnosis of Multiple-Voltage Design With Bridge Defect. 406-416 - Yu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang:
Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation. 417-425 - Irith Pomeranz, Sudhakar M. Reddy:
Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits. 426-432 - Haiqiong Yao, Hao Zheng:
Automated Interface Refinement for Compositional Verification. 433-446 - Angelo Brambilla
Determination of Floquet Exponents for Small-Signal Analysis of Nonlinear Periodic Circuits. 447-451 - Eunjoo Choi, Changsik Shin, Youngsoo Shin:
ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits. 451-456 - Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Spare Cells With Constant Insertion for Engineering Change. 456-460 - Aviral Shrivastava
Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures. 461-465
Volume 28, Number 4, April 2009
- Pramod Kumar Meher:
Extended Sequential Logic for Synchronous Circuit Optimization and Its Applications. 469-477 - Behnam Amelifard, Farzan Fallah, Massoud Pedram:
Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi Channel Lengths. 478-489 - Wei Dong, Peng Li:
A Parallel Harmonic-Balance Approach to Steady-State and Envelope-Following Simulation of Driven and Autonomous Circuits. 490-501 - Yongfeng Feng, H. Alan Mantooth:
Algorithms for Automatic Model Topology Formulation. 502-515 - Vittorio Rizzoli, Franco Mastri, Alessandra Costanzo
Harmonic-Balance Algorithms for the Circuit-Level Nonlinear Analysis of UWB Receivers in the Presence of Interfering Signals. 516-527 - Muhammet Mustafa Ozdal, Martin D. F. Wong
Archer: A History-Based Global Routing Algorithm. 528-540 - Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto
Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise. 541-553 - Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil D. Dutt
Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications. 554-567 - Jungsoo Kim, Seungyong Oh, Sungjoo Yoo, Chong-Min Kyung:
An Analytical Dynamic Scaling of Supply Voltage and Body Bias Based on Parallelism-Aware Workload and Runtime Distribution. 568-581 - Haralampos-G. D. Stratigopoulos, Salvador Mir, Ahcène Bounceur:
Evaluation of Analog/RF Test Measurements at the Design Stage. 582-590 - Yu Hu, Satyaki Das, Steven Trimberger, Lei He:
Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate. 591-595 - Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu:
An Improved Soft-Error Rate Measurement Technique. 596-600 - Shuo Wang, Lei Wang:
Analysis of Deskew Signaling Via Adaptive Timing. 601-605
Volume 28, Number 5, May 2009
- Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Automated Design and Optimization of Low-Noise Oscillators. 609-622 - Yang Xu, Kan-Lin Hsiung, Xin Li, Lawrence T. Pileggi, Stephen P. Boyd:
Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty. 623-637 - Yee Jern Chong, Sri Parameswaran
Custom Floating-Point Unit Generation for Embedded Systems. 638-650 - Pritha Banerjee
Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs. 651-661 - Roberto Cordone, Francesco Redaelli, Massimo Redaelli, Marco D. Santambrogio
Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs. 662-675 - Gaurav Dhiman, Tajana Simunic Rosing:
System-Level Power Management Using Online Learning. 676-689 - Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang
Voltage-Island Partitioning and Floorplanning Under Timing Constraints. 690-702 - Daniel Große
Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. 703-715 - Sying-Jyan Wang
Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint. 716-727 - Andrew DeOrio, Adam Bauserman, Valeria Bertacco, Beth Isaksen:
Inferno: Streamlining Verification With Inferred Semantics. 728-741 - Omid Sarbishei, Mahmoud Tabandeh, Bijan Alizadeh, Masahiro Fujita:
A Formal Approach for Debugging Arithmetic Circuits. 742-754 - Abdallatif S. Abu-Issa, Steven F. Quigley:
Bit-Swapping LFSR and Scan-Chain Ordering: A Novel Technique for Peak- and Average-Power Reduction in Scan-Based BIST. 755-759 - Kunihiro Fujiyoshi, Hidenori Kawai, Keisuke Ishihara:
A Tree Based Novel Representation for 3D-Block Packing. 759-764 - Chao-Wen Tzeng, Han-Chia Cheng, Shi-Yu Huang:
Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects. 764-769 - Yifan Wang, Stefan Joeres, Ralf Wunderlich, Stefan Heinen:
Modeling Approaches for Functional Verification of RF-SoCs: Limits and Future Requirements. 769-773
Volume 28, Number 6, June 2009
- Giovanni De Micheli:
An Outlook on Design Technologies for Future Integrated Systems. 777-790 - Mark Po-Hung Lin
Analog Placement Based on Symmetry-Island Formulation. 791-804 - Giovanni Agosta
A Transform-Parametric Approach to Boolean Matching. 805-817 - Shiyan Hu
Gate Sizing for Cell-Library-Based Designs. 818-825 - Haitao Dai, Ronald W. Knepper:
Modeling and Experimental Measurement of Active Substrate-Noise Suppression in Mixed-Signal 0.18µm BiCMOS Technology. 826-836 - Suprio Das, Shamik Sural
Resistance Estimation for Lateral Power Arrays Through Accurate Netlist Generation. 837-845 - Ki Jin Han
Inductance and Resistance Calculations in Three-Dimensional Packaging Using Cylindrical Conduction-Mode Basis Functions. 846-859 - Zyad Hassan, Nicholas Allec, Li Shang, Robert P. Dick, V. Venkatraman, Ronggui Yang:
Multiscale Thermal Analysis for Nanometer-Scale Integrated Circuits. 860-873 - Khaled R. Heloue, Navid Azizi, Farid N. Najm:
Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation. 874-887 - Behnam Amelifard, Massoud Pedram:
Optimal Design of the Power-Delivery Network for Multiple Voltage-Island System-on-Chips. 888-900 - Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin:
Using Data Compression for Increasing Memory System Utilization. 901-914 - Michele Favalli
Testing Resistive Opens and Bridging Faults Through Pulse Propagation. 915-925 - Minje Jun, Sungjoo Yoo, Eui-Young Chung:
Topology Synthesis of Cascaded Crossbar Switches. 926-930
Volume 28, Number 7, July 2009
- Alberto L. Sangiovanni-Vincentelli, Marco Di Natale
Challenges and Solutions in the Development of Automotive Systems. 937-940 - Sinem Coleri Ergen
The Tire as an Intelligent Sensor. 941-955 - Roman Obermaisser, Christian El Salloum, Bernhard Huber, Hermann Kopetz:
From a Federated to an Integrated Automotive Architecture. 956-965 - Reinhard Wilhelm, Daniel Grund, Jan Reineke, Marc Schlickling, Markus Pister, Christian Ferdinand:
Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems. 966-978 - Simon Schliecker, Jonas Rox, Mircea Negrean, Kai Richter, Marek Jersak, Rolf Ernst:
System Level Performance Analysis for Real-Time Automotive Multicore and Network Architectures. 979-992 - Erkan Acar, Sule Ozev:
Low-Cost Characterization and Calibration of RF Integrated Circuits through I - Q Data Analysis. 993-1005 - Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan:
ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction. 1006-1016 - Sonali Chouhan, Ranjan Bose, M. Balakrishnan:
A Framework for Energy-Consumption-Based Design Space Exploration for Wireless Sensor Nodes. 1017-1024 - Deniz Dal
Power Optimization With Power Islands Synthesis. 1025-1037 - S. Mukhopadhyay:
A Generic Data-Driven Nonparametric Framework for Variability Analysis of Integrated Circuits in Nanometer Technologies. 1038-1046 - Navin Srivastava, Roberto Suaya, Kaustav Banerjee:
Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate. 1047-1060 - Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini
A Novel Table-Based Approach for Design of FinFET Circuits. 1061-1070 - Jia Wang, Debasish Das, Hai Zhou:
Gate Sizing by Lagrangian Relaxation Revisited. 1071-1084 - Lin Xie, Azadeh Davoodi, Jun Zhang, Tai-Hsuan Wu:
Adjustment-Based Modeling for Timing Analysis Under Variability. 1085-1095 - Debjit Sinha, Alex Rubin, Chandu Visweswariah, Frank Borkam, Gregory Schaeffer, Soroush Abbaspour:
Feasible Aggressor-Set Identification Under Constraints for Maximum Coupling Noise. 1096-1100 - Dong Xiang, Dianwei Hu, Qiang Xu
Low-Power Scan Testing for Test Data Compression Using a Routing-Driven Scan Architecture. 1101-1105 - Yang Yi, R. Wenzel, Vivek Sarin, Weiping Shi:
Inductance Extraction for Interconnects in the Presence of Nonlinear Magnetic Materials. 1106-1110
Volume 28, Number 8, August 2009
- Chen-Hsuan Lin, Chun-Yao Wang, Yung-Chih Chen:
Dependent-Latch Identification in Reachable State Space. 1113-1126 - Nilanjan Banerjee, Georgios Karakonstantis, Jung Hwan Choi, Chaitali Chakrabarti, Kaushik Roy:
Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering. 1127-1137 - Duo Chen, Dan Jiao:
Time-Domain Orthogonal Finite-Element Reduction-Recovery Method for Electromagnetics-Based Analysis of Large-Scale Integrated Circuit and Package Problems. 1138-1149 - Ibrahim M. Elfadel
Convergence of Transverse Waveform Relaxation for the Electrical Analysis of Very Wide Transmission Line Buses. 1150-1161 - Trent McConaghy, Georges G. E. Gielen
Template-Free Symbolic Performance Modeling of Analog Circuits via Canonical-Form Functions and Genetic Programming. 1162-1175 - Amith Singhee, Rob A. Rutenbar
Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design. 1176-1189 - Zhiyu Zeng, Peng Li:
Locality-Driven Parallel Power Grid Optimization. 1190-1200 - Qunzeng Liu, Sachin S. Sapatnekar
A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations. 1201-1212 - Lih-Yih Chiou, Yi-Siou Chen, Chih-Hsien Lee:
System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm. 1213-1223 - Xiaoke Qin, Prabhat Mishra
A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression. 1224-1236 - Roshan Weerasekera
Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints. 1237-1250 - Zhanglei Wang, Krishnendu Chakrabarty
Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip. 1251-1264 - Shih-Hsu Huang, Chun-Hua Cheng:
Minimum-Period Register Binding. 1265-1269 - Urban Ingelsson, Bashir M. Al-Hashimi, S. Saqib Khursheed, Sudhakar M. Reddy, Peter Harrod:
Process Variation-Aware Test for Resistive Bridges. 1269-1274 - Myeongjin Kim, Eui-Young Chung, Sungroh Yoon:
High-Speed Post-Layout Logic Simulation Using Quasi-Static Clock Event Evaluation. 1274-1278
Volume 28, Number 9, September 2009
- Trent McConaghy, Pieter Palmers, Michiel Steyaert
Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical Building Blocks and Structural Homotopy. 1281-1294 - Ping-Hung Yuh, Sachin S. Sapatnekar
A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips. 1295-1306 - Jie Zhang, Nishant Patil, Subhasish Mitra:
Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits. 1307-1320 - Maciej J. Ciesielski, Daniel Gomez-Prado, Qian Ren, Jérémie Guillot, Emmanuel Boutillon:
Optimization of Data-Flow Computations Using Canonical TED Representation. 1321-1333 - Sung-Yong Bang, Kwanhu Bang, Sungroh Yoon, Eui-Young Chung:
Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling. 1334-1347 - Wanping Zhang, Wenjian Yu, Xiang Hu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng:
Efficient Power Network Analysis Considering Multidomain Clock Gating. 1348-1358 - Emad Gad
A-Stable and L-Stable High-Order Integration Methods for Solving Stiff Differential Equations. 1359-1372 - Mohit Pathak, Sung Kyu Lim
Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs. 1373-1386 - Ehab Anis Daoud, Nicola Nicolici:
Real-Time Lossless Compression for Silicon Debug. 1387-1400 - Sunghoon Chun, Taejin Kim, Sungho Kang:
ATPG-XP: Test Generation for Maximal Crosstalk-Induced Faults. 1401-1413 - Jinjun Xiong
Optimal Test Margin Computation for At-Speed Structural Test. 1414-1423 - Irith Pomeranz, Sudhakar M. Reddy:
Forward-Looking Reverse Order Fault Simulation for n -Detection Test Sets. 1424-1428 - Ivica Stevanovic, Colin C. McAndrew:
Quadratic Backward Propagation of Variance for Nonlinear Statistical Circuit Modeling. 1428-1432
Volume 28, Number 10, October 2009
- Josep Carmona
Elastic Circuits. 1437-1455 - Davit Harutyunyan, Joost Rommes, E. Jan W. ter Maten, Wil H. A. Schilders:
Simulation of Mutually Coupled Oscillators Using Nonlinear Phase Macromodels. 1456-1466 - Bradley N. Bond, Luca Daniel:
Stable Reduced Models for Nonlinear Descriptor Systems Through Piecewise-Linear Approximation and Projection. 1467-1480 - Sourajeet Roy, Anestis Dounavis:
Closed-Form Delay and Crosstalk Models for RLC On-Chip Interconnects Using a Matrix Rational Approximation. 1481-1492 - Rajat Subhra Chakraborty, Swarup Bhunia
HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection. 1493-1502 - Ayse Kivilcim Coskun, Tajana Simunic Rosing, Kenny C. Gross:
Utilizing Predictors for Efficient Thermal Management in Multiprocessor SoCs. 1503-1516 - Andreas Gerstlauer, Christian Haubelt
Electronic System-Level Synthesis Methodologies. 1517-1530 - Wan Yeon Lee, Hyogon Kim, Heejo Lee:
Maximum-Utility Scheduling of Operation Modes With Probabilistic Task Execution Times Under Energy Constraints. 1531-1544 - Sung-Boem Park, Ted Hong, Subhasish Mitra:
Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA). 1545-1558 - Ravishankar Rao, Sarma B. K. Vrudhula:
Fast and Accurate Prediction of the Steady-State Throughput of Multicore Processors Under Thermal Constraints. 1559-1572 - Nisar Ahmed, Mohammad Tehranipoor:
A Novel Faster-Than-at-Speed Transition-Delay Test Method Considering IR-Drop Effects. 1573-1582 - Sying-Jyan Wang
High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability. 1583-1596 - Sean Safarpour, Andreas G. Veneris:
Automated Design Debugging With Abstraction and Refinement. 1597-1608
Volume 28, Number 11, November 2009
- Stephane Bronckers, Karen Scheir, Geert Van der Plas
A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems. 1613-1626 - Trent McConaghy, Georges G. E. Gielen
Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy. 1627-1640 - Zuochang Ye, Zhenhai Zhu, Joel R. Phillips:
Incremental Large-Scale Electrostatic Analysis. 1641-1653 - Quan Chen, Hoi Wai Choi
Robust Simulation Methodology for Surface-Roughness Loss in Interconnect and Package Modelings. 1654-1665 - Tai-Hsuan Wu, Azadeh Davoodi:
PaRS: Parallel and Near-Optimal Grid-Based Cell Sizing for Library-Based Design. 1666-1678 - Tan Yan, Martin D. F. Wong
BSG-Route: A Length-Constrained Routing Scheme for General Planar Topology. 1679-1690 - Andrea Alimonda, Salvatore Carta, Andrea Acquaviva, Alessandro Pisano
A Feedback-Based Approach to DVFS in Data-Flow Applications. 1691-1704 - Edward T.-H. Chu, Tai-Yi Huang, Yu-Che Tsai:
An Optimal Solution for the Heterogeneous Multiprocessor Single-Level Voltage-Setup Problem. 1705-1718 - Aviral Shrivastava
A Software-Only Solution to Use Scratch Pads for Stack Data. 1719-1727 - Nicholas Callegari, Pouria Bastani, Li-C. Wang
A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing Mismatch. 1728-1741 - Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low-Power Scan Operation in Test Compression Environment. 1742-1755 - Chao-Wen Tzeng, Shi-Yu Huang:
QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test. 1756-1766 - Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase:
Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment. 1767-1776 - Lerong Cheng, Puneet Gupta
Efficient Additive Statistical Leakage Estimation. 1777-1781
Volume 28, Number 12, December 2009
- Enrico Macii:
Editorial. 1785 - Alex Orailoglu, Laura Pozzi:
Guest Editorial Special Section on the IEEE Symposium on Application Specific Processors 2008. 1786-1787 - Marcela Zuluaga, Nigel P. Topham:
Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions. 1788-1801 - Josef B. Spjut, Andrew E. Kensler, Daniel M. Kopta, Erik Brunvand:
TRaX: A Multicore Hardware Architecture for Real-Time Ray Tracing. 1802-1815 - Gianluca Palermo
ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration. 1816-1829 - Wei Han, Ying Yi, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet T. Erdogan
Multicore Architectures With Dynamically Reconfigurable Array Processors for Wireless Broadband Technologies. 1830-1843 - Jiajia Chen, Chip-Hong Chang
High-Level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier. 1844-1856 - Giovanni Beltrame, Luca Fossati, Donatella Sciuto
ReSP: A Nonintrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration. 1857-1869 - Fabrizio Mulas, David Atienza
Thermal Balancing Policy for Multiprocessor Stream Computing Platforms. 1870-1882 - Zhigang Jiang, Sandeep K. Gupta:
Threshold Testing: Improving Yield for Nanoscale VLSI. 1883-1895 - Ivica Stevanovic
Corrections to "Quadratic Backward Propagation of Variance for Nonlinear Statistical Circuit Modeling" [Sep 09 1428-1432]. 1896
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