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2020 – today
- 2024
- [j38]Sojung Yim
, Sang-Min Baek
Development of the sub-10 cm, sub-100 g jumping-crawling robot. Intell. Serv. Robotics 17(1): 19-32 (2024) - [j37]Amir Firouzeh
Perching and Grasping Using a Passive Dynamic Bioinspired Gripper. IEEE Trans. Robotics 40: 213-225 (2024) - [c70]Minsang Yu, Minuk Hong, Sugil Lee, Seungsu Kim, Jongeun Lee:
PyAIM: Pynq-Based Scalable Analog In-Memory Computing Prototyping Platform. AICAS 2024: 174-178 - [c69]Minjoon Song, Faaiz Asim, Jongeun Lee:
Extending Neural Processing Unit and Compiler for Advanced Binarized Neural Networks. ASPDAC 2024: 115-120 - [c68]Hyunsik Jeon
Cold-start Bundle Recommendation via Popularity-based Coalescence and Curriculum Heating. WWW 2024: 3277-3286 - 2023
- [j36]Seon Ha
Kernel Code Integrity Protection at the Physical Address Level on RISC-V. IEEE Access 11: 62358-62367 (2023) - [j35]Sugil Lee
Offline Training-Based Mitigation of IR Drop for ReRAM-Based Deep Neural Network Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 521-532 (2023) - [j34]Chenghao Quan
Training-Free Stuck-At Fault Mitigation for ReRAM-Based Deep Learning Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2174-2186 (2023) - [j33]Azat Azamat
Partial Sum Quantization for Reducing ADC Size in ReRAM-Based Neural Network Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4897-4908 (2023) - [c67]Jaewoo Park
NTT-PIM: Row-Centric Architecture and Mapping for Efficient Number-Theoretic Transform on PIM. DAC 2023: 1-6 - [c66]Jaewoo Park, Chenghao Quan, Hyungon Moon, Jongeun Lee:
Hyperdimensional Computing as a Rescue for Efficient Privacy-Preserving Machine Learning-as-a-Service. ICCAD 2023: 1-8 - [c65]Hyeonjin Jo, Chaerin Sim, Jaewoo Park, Jongeun Lee:
Accelerating Transformers with Fourier-Based Attention for Efficient On-Device Inference. ISOCC 2023: 203-204 - [c64]Hyunsik Jeon, Jongjin Kim, Jaeri Lee, Jong-eun Lee, U Kang:
Aggregately Diversified Bundle Recommendation via Popularity Debiasing and Configuration-Aware Reranking. PAKDD (3) 2023: 348-360 - [i4]Hyunsik Jeon, Jong-eun Lee, Jeongin Yun, U Kang:
Accurate Cold-start Bundle Recommendation via Popularity-based Coalescence and Curriculum Heating. CoRR abs/2310.03813 (2023) - [i3]Jaewoo Park, Chenghao Quan, Hyungon Moon, Jongeun Lee:
Hyperdimensional Computing as a Rescue for Efficient Privacy-Preserving Machine Learning-as-a-Service. CoRR abs/2310.06840 (2023) - [i2]Jaewoo Park, Sugil Lee, Jongeun Lee:
NTT-PIM: Row-Centric Architecture and Mapping for Efficient Number-Theoretic Transform on PIM. CoRR abs/2310.09715 (2023) - 2022
- [j32]Hyoungshin Choi
Diagnosis-informed connectivity subtyping discovers subgroups of autism with reproducible symptom profiles. NeuroImage 256: 119212 (2022) - [j31]Jungi Lee, Jongeun Lee
Specializing CGRAs for Light-Weight Convolutional Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3387-3399 (2022) - [j30]Jooyeon Choi, Hyeonuk Sim, Sangyun Oh
MLogNet: A Logarithmic Quantization-Based Accelerator for Depthwise Separable Convolution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5220-5231 (2022) - [c63]Chenghao Quan, Mohammed E. Fouda, Sugil Lee, Jongeun Lee:
Multi-Fidelity Nonideality Simulation and Evaluation Framework for Resistive Neuromorphic Computing. IEEECONF 2022: 1152-1156 - [c62]Faaiz Asim, Jaewoo Park, Azat Azamat, Jongeun Lee:
Centered Symmetric Quantization for Hardware-Efficient Low-Bit Neural Networks. BMVC 2022: 538 - [c61]Hyeshin Chu, Joohee Kim, Seongouk Kim, Hongkyu Lim, Hyunwook Lee
An Empirical Study on How People Perceive AI-generated Music. CIKM 2022: 304-314 - [c60]Sangyun Oh
Non-uniform Step Size Quantization for Accurate Post-training Quantization. ECCV (11) 2022: 658-673 - [c59]Azat Azamat, Jaewoo Park
Squeezing Accumulators in Binary Neural Networks for Extremely Resource-Constrained Applications. ICCAD 2022: 141:1-141:7 - [c58]Sugil Lee, Mohammed E. Fouda, Jongeun Lee, Ahmed M. Eltawil
Accurate Prediction of ReRAM Crossbar Performance Under I-V Nonlinearity and IR Drop. ICCD 2022: 9-16 - 2021
- [c57]Sangyun Oh, Hyeonuk Sim, Sugil Lee, Jongeun Lee:
Automated Log-Scale Quantization for Low-Cost Deep Neural Networks. CVPR 2021: 742-751 - [c56]Jungi Lee, Jongeun Lee:
NP-CGRA: Extending CGRAs for Efficient Processing of Light-weight Deep Neural Networks. DATE 2021: 1408-1413 - [c55]Giju Jung, Mohammed E. Fouda, Sugil Lee, Jongeun Lee, Ahmed M. Eltawil
Cost- and Dataset-free Stuck-at Fault Mitigation for ReRAM-based Deep Learning Accelerators. DATE 2021: 1733-1738 - [c54]Azat Azamat, Faaiz Asim, Jongeun Lee:
Quarry: Quantization-based ADC Reduction for ReRAM-based Deep Neural Network Accelerators. ICCAD 2021: 1-7 - [c53]Sugil Lee, Mohammed E. Fouda, Jongeun Lee, Ahmed M. Eltawil
Fast and Low-Cost Mitigation of ReRAM Variability for Deep Learning Applications. ICCD 2021: 269-276 - 2020
- [j29]Sangyun Oh
RRNet: Repetition-Reduction Network for Energy Efficient Depth Estimation. IEEE Access 8: 106097-106108 (2020) - [j28]Mohammed E. Fouda
IR-QNN Framework: An IR Drop-Aware Offline Training of Quantized Crossbar Arrays. IEEE Access 8: 228392-228408 (2020) - [j27]Jongeun Lee
CaseCrawler: A Lightweight and Low-Profile Crawling Phone Case Robot. IEEE Robotics Autom. Lett. 5(4): 5858-5865 (2020) - [c52]Sugil Lee, Giju Jung, Mohammed E. Fouda, Jongeun Lee, Ahmed M. Eltawil
Learning to Predict IR Drop with Effective Training for ReRAM-based Neural Network Hardware. DAC 2020: 1-6 - [c51]Segi Lee, Sugil Lee, Jongeun Lee, Jong-Moon Choi, Do-Wan Kwon, Seung-Kwang Hong, Kee-Won Kwon:
Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor. ACM Great Lakes Symposium on VLSI 2020: 427-432 - [c50]Hyeonuk Sim, Jooyeon Choi, Jongeun Lee:
SparTANN: sparse training accelerator for neural networks with threshold-based sparsification. ISLPED 2020: 211-216
2010 – 2019
- 2019
- [j26]Hyeonuk Sim, Jongeun Lee:
Cost-effective stochastic MAC circuits for deep neural networks. Neural Networks 117: 152-162 (2019) - [j25]Sugil Lee
Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 888-897 (2019) - [c49]Daewoo Kim, Sugil Lee, Jongeun Lee:
On-chip memory optimization for high-level synthesis of multi-dimensional data on FPGA. ASP-DAC 2019: 243-248 - [c48]Hyeon Uk Sim, Jongeun Lee:
Log-quantized stochastic computing for memory and computation efficient DNNs. ASP-DAC 2019: 280-285 - [c47]Hyeon Uk Sim, Jason Helge Anderson, Jongeun Lee:
XOMA: exclusive on-chip memory architecture for energy-efficient deep learning acceleration. ASP-DAC 2019: 651-656 - [c46]Aidyn Zhakatayev, Jongeun Lee:
Efficient FPGA implementation of local binary convolutional neural network. ASP-DAC 2019: 699-704 - [c45]Sugil Lee, Hyeon Uk Sim, Jooyeon Choi, Jongeun Lee:
Successive Log Quantization for Cost-Efficient Neural Networks Using Stochastic Computing. DAC 2019: 7 - [i1]Sangyun Oh, Hye-Jin S. Kim, Jongeun Lee, Junmo Kim:
RRNet: Repetition-Reduction Network for Energy Efficient Decoder of Depth Estimation. CoRR abs/1907.09707 (2019) - 2018
- [j24]Aidyn Zhakatayev
An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3056-3066 (2018) - [c44]Hyeon Uk Sim, Saken Kenzhegulov, Jongeun Lee:
DPS: dynamic precision scaling for stochastic computing-based deep neural networks. DAC 2018: 13:1-13:6 - [c43]Aidyn Zhakatayev, Sugil Lee, Hyeon Uk Sim, Jongeun Lee:
Sign-magnitude SC: getting 10X accuracy for free in stochastic computing for deep neural networks. DAC 2018: 158:1-158:6 - [c42]Jin Hee Kim, Jongeun Lee, Jason Helge Anderson:
FPGA Architecture Enhancements for Efficient BNN Implementation. FPT 2018: 214-221 - [c41]S. Alexander Chin, Kuang Ping Niu, Matthew J. P. Walker, Shizhang Yin, Alexander Mertens, Jongeun Lee, Jason Helge Anderson:
Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework. ISPD 2018: 48-55 - [c40]Mohammed E. Fouda, Jongeun Lee, Ahmed M. Eltawil
Overcoming Crossbar Nonidealities in Binary Neural Networks Through Learning. NANOARCH 2018: 31-33 - 2017
- [j23]Sangyun Oh, Hongsik Lee, Jongeun Lee
Efficient Execution of Stream Graphs on Coarse-Grained Reconfigurable Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(12): 1978-1988 (2017) - [c39]Hyeon Uk Sim, Dong Nguyen, Jongeun Lee, Kiyoung Choi:
Scalable stochastic-computing accelerator for convolutional neural networks. ASP-DAC 2017: 696-701 - [c38]Hyeon Uk Sim, Jongeun Lee:
A New Stochastic Computing Multiplier with Application to Deep Convolutional Neural Networks. DAC 2017: 29:1-29:6 - [c37]Dong Nguyen, Daewoo Kim, Jongeun Lee:
Double MAC: Doubling the performance of convolutional neural networks on modern FPGAs. DATE 2017: 890-893 - [c36]Atul Rahman, Sangyun Oh, Jongeun Lee, Kiyoung Choi:
Design space exploration of FPGA accelerators for convolutional neural networks. DATE 2017: 1147-1152 - [c35]Daewoo Kim, Mansureh S. Moghaddam, Hossein Moradian, Hyeon Uk Sim, Jongeun Lee, Kiyoung Choi:
FPGA implementation of convolutional neural network based on stochastic computing. FPT 2017: 287-290 - [c34]Joonsang Yu, Kyounghoon Kim, Jongeun Lee, Kiyoung Choi:
Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks. ICCD 2017: 105-112 - [c33]Jongeun Lee, Gwang-Pil Jung, Kyu-Jin Cho:
Bio-inspired Design of a Double-Sided Crawling Robot. Living Machines 2017: 562-566 - 2016
- [j22]Hyeon Uk Sim, Hongsik Lee, Seongseok Seo, Jongeun Lee:
Mapping Imperfect Loops to Coarse-Grained Reconfigurable Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7): 1092-1104 (2016) - [j21]Hyeon Uk Sim, Atul Rahman, Jongeun Lee:
Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2799-2802 (2016) - [c32]Kyounghoon Kim, Jongeun Lee, Kiyoung Choi:
An energy-efficient random number generator for stochastic circuits. ASP-DAC 2016: 256-261 - [c31]Dong Nguyen, Jongeun Lee:
Communication-aware mapping of stream graphs for multi-GPU platforms. CGO 2016: 94-104 - [c30]Kyounghoon Kim, Jungki Kim, Joonsang Yu, Jungwoo Seo, Jongeun Lee, Kiyoung Choi:
Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks. DAC 2016: 124:1-124:6 - [c29]Atul Rahman, Jongeun Lee, Kiyoung Choi:
Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array. DATE 2016: 1393-1398 - [c28]Jungwoo Seo, Joonsang Yu, Jongeun Lee, Kiyoung Choi:
A new approach to binarizing neural networks. ISOCC 2016: 77-78 - 2015
- [c27]Hongsik Lee, Dong Nguyen, Jongeun Lee:
Optimizing stream program performance on CGRA-based systems. DAC 2015: 110:1-110:6 - 2014
- [j20]Jongeun Lee, Steve Goddard, Chin-Fu Kuo:
Design and optimization for embedded and real-time computing systems and applications. J. Syst. Archit. 60(2): 151 (2014) - [j19]Jongeun Lee, Seongseok Seo, Jong Kyung Paek, Kiyoung Choi:
Configurable range memory for effective data reuse on programmable accelerators. ACM Trans. Design Autom. Electr. Syst. 19(2): 13:1-13:22 (2014) - [c26]Jongeun Lee, Seongseok Seo, Hongsik Lee, Hyeon Uk Sim:
Flattening-based mapping of imperfect loop nests for CGRAs? CODES+ISSS 2014: 9:1-9:10 - [c25]Toan X. Mai, Jongeun Lee:
Efficient Software-Based Runtime Binary Translation for Coarse-Grained Reconfigurable Architectures. IPDPS Workshops 2014: 132-140 - [c24]Jinyong Lee, Jongwon Lee, Jongeun Lee, Yunheung Paek:
Improving performance of loops on DIAM-based VLIW architectures. LCTES 2014: 135-144 - 2013
- [j18]Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Seok-Hun Hyun, Hanki Jeoung, Ki Won Lee, Jun-Seok Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Byungchul Kim, Jung-Hwan Choi, Seong-Jin Jang, Chi-Wook Kim, Jung-Bae Lee, Joo-Sun Choi:
A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme. IEEE J. Solid State Circuits 48(1): 168-177 (2013) - [j17]Yeonghun Jeong, Seongseok Seo, Jongeun Lee:
Evaluator-executor transformation for efficient pipelining of loops with conditionals. ACM Trans. Archit. Code Optim. 10(4): 62:1-62:23 (2013) - [j16]Jongeun Lee, Aviral Shrivastava
Software-based register file vulnerability reduction for embedded processors. ACM Trans. Embed. Comput. Syst. 13(1s): 38:1-38:20 (2013) - [j15]Jonghee W. Yoon, Jongeun Lee, Sanghyun Park, Yongjoo Kim, Jinyong Lee, Yunheung Paek, Doosan Cho:
Architecture customization of on-chip reconfigurable accelerators. ACM Trans. Design Autom. Electr. Syst. 18(4): 52:1-52:22 (2013) - [c23]Jongeun Lee, Yeonghun Jeong, Sungsok Seo:
Fast shared on-chip memory architecture for efficient hybrid computing with CGRAs. DATE 2013: 1575-1578 - [c22]Kyuseung Han, Kiyoung Choi, Jongeun Lee:
Compiling control-intensive loops for CGRAs with state-based full predication. DATE 2013: 1579-1582 - 2012
- [j14]Yongjoo Kim, Jongeun Lee, Toan X. Mai, Yunheung Paek:
Improving performance of nested loops on reconfigurable array processors. ACM Trans. Archit. Code Optim. 8(4): 32:1-32:23 (2012) - [j13]Jongeun Lee, Aviral Shrivastava
PICA: Processor Idle Cycle Aggregation for Energy-Efficient Embedded Systems. ACM Trans. Embed. Comput. Syst. 11(2): 26:1-26:27 (2012) - [j12]Fei Hong, Aviral Shrivastava
Return Data Interleaving for Multi-Channel Embedded CMPs Systems. IEEE Trans. Very Large Scale Integr. Syst. 20(7): 1351-1354 (2012) - [c21]Yongjoo Kim, Jongeun Lee, Jinyong Lee, Toan X. Mai, Ingoo Heo, Yunheung Paek:
Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture. ARC 2012: 40-52 - [c20]Toan X. Mai, Jongeun Lee:
Software-managed automatic data sharing for Coarse-Grained Reconfigurable coprocessors. FPT 2012: 277-284 - [c19]Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Hanki Jeoung, Ki Won Lee, Junsuk Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Jang Seok Choi, Byung-Sick Moon, Jung-Hwan Choi, Byungchul Kim, Seong-Jin Jang, Joo-Sun Choi, Kyungseok Oh:
A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme. ISSCC 2012: 38-40 - 2011
- [j11]Jonghee M. Youn
Fast graph-based instruction selection for multi-output instructions. Softw. Pract. Exp. 41(6): 717-736 (2011) - [j10]Jongeun Lee, Aviral Shrivastava
Static Analysis of Register File Vulnerability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4): 607-616 (2011) - [j9]Yongjoo Kim, Jongeun Lee, Aviral Shrivastava
High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1599-1609 (2011) - [j8]Yongjoo Kim, Jongeun Lee, Aviral Shrivastava
Memory access optimization in compilation for coarse-grained reconfigurable architectures. ACM Trans. Design Autom. Electr. Syst. 16(4): 42:1-42:27 (2011) - [c18]Jonghee W. Yoon, Jongeun Lee, Jaewan Jung, Sanghyun Park, Yongjoo Kim, Yunheung Paek, Doosan Cho:
I2CRF: Incremental interconnect customization for embedded reconfigurable fabrics. DATE 2011: 1346-1351 - [c17]Jong Kyung Paek, Jong-eun Lee, Kiyoung Choi:
CRM: Configurable Range Memory for Fast Reconfigurable Computing. IPDPS Workshops 2011: 158-165 - 2010
- [j7]Jong Kyung Paek, Kiyoung Choi, Jong-eun Lee:
Binary acceleration using coarse-grained reconfigurable architecture. SIGARCH Comput. Archit. News 38(4): 33-39 (2010) - [j6]Jongeun Lee, Aviral Shrivastava
A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1018-1027 (2010) - [c16]Yongjoo Kim, Jongeun Lee, Aviral Shrivastava
Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays. HiPEAC 2010: 171-185 - [c15]Yongjoo Kim, Jongeun Lee, Aviral Shrivastava
Operation and data mapping for CGRAs with multi-bank memory. LCTES 2010: 17-26 - [c14]Aviral Shrivastava
Cache vulnerability equations for protecting data in embedded processor caches from soft errors. LCTES 2010: 143-152
2000 – 2009
- 2009
- [j5]Aviral Shrivastava
A Software-Only Solution to Use Scratch Pads for Stack Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1719-1727 (2009) - [c13]Arun Kannan, Aviral Shrivastava
A software solution for dynamic stack management on scratch pad memory. ASP-DAC 2009: 612-617 - [c12]Jongeun Lee, Aviral Shrivastava
Compiler-managed register file protection for energy-efficient soft error reduction. ASP-DAC 2009: 618-623 - [c11]Sai Krishna Mylavarapu, Siddharth Choudhuri, Aviral Shrivastava
FSAF: File system aware flash translation layer for NAND Flash Memories. DATE 2009: 399-404 - [c10]Jongeun Lee, Aviral Shrivastava:
Static analysis to mitigate soft errors in register files. DATE 2009: 1367-1372 - [c9]Jongeun Lee, Aviral Shrivastava
A compiler optimization to reduce soft errors in register files. LCTES 2009: 41-49 - 2008
- [j4]Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures. Int. J. Embed. Syst. 3(3): 119-127 (2008) - [c8]Geonhyeok Go, Sujung Han, Jongeun Lee, Yuri Choi, Bowen Sun, Youngwoo Park, Donggi Jung, Sungjae Hwang, Chang-Young Lim:
Hanmadang: entertainment systems for massive face-to-face interaction. Advances in Computer Entertainment Technology 2008: 397 - [c7]Jongeun Lee, Aviral Shrivastava
Static analysis of processor stall cycle aggregation. CODES+ISSS 2008: 25-30 - [c6]Amit Pabalkar, Aviral Shrivastava
SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories. HiPC 2008: 569-582 - 2007
- [j3]Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
Instruction set synthesis with efficient instruction encoding for configurable processors. ACM Trans. Design Autom. Electr. Syst. 12(1): 9:1-9:37 (2007) - 2004
- [j2]Seung Hee Ho, Sun Ha Jee
Analysis on risk factors for cervical cancer using induction technique. Expert Syst. Appl. 27(1): 97-105 (2004) - 2003
- [j1]Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
Compilation Approach for Coarse-Grained Reconfigurable Architectures. IEEE Des. Test Comput. 20(1): 26-33 (2003) - [c5]Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures. ASAP 2003: 172-182 - [c4]Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
Energy-efficient instruction set synthesis for application-specific processors. ISLPED 2003: 330-333 - [c3]Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
An algorithm for mapping loops onto coarse-grained reconfigurable architectures. LCTES 2003: 183-188 - 2002
- [c2]Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
Efficient instruction encoding for automatic instruction set design of configurable ASIPs. ICCAD 2002: 649-654 - 2000
- [c1]Sungjoo Yoo, Jong-eun Lee, Jinyong Jung, Kyungseok Rha, Youngchul Cho, Kiyoung Choi:
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor. DATE 2000: 663-668
Coauthor Index
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