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Roberto Suaya
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2010 – 2019
- 2019
- [c13]Guillermo H. Makar, Francisco J. Badenas, Roberto G. Simone, Alejandro Furfaro, Kenneth S. Stevens, Roberto Suaya:
Low Power SPI Design Based on Relative Timing Techniques. ICECS 2019: 166-169 - 2013
- [c12]Shomit Das, Georgios Manetas, Kenneth S. Stevens, Roberto Suaya:
Leveraging the geometric properties of on-chip transmission line structures to improve interconnect performance: A case study in 65nm. NOCS 2013: 1-2 - 2012
- [j6]Chuan Xu, Navin Srivastava, Roberto Suaya, Kaustav Banerjee:
Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(11): 1698-1710 (2012) - [c11]Zohaib Mahmood, Roberto Suaya, Luca Daniel:
An efficient framework for passive compact dynamical modeling of multiport linear systems. DATE 2012: 1203-1208 - 2010
- [j5]Navin Srivastava, Chuan Xu, Roberto Suaya, Kaustav Banerjee:
Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 849 (2010) - [c10]Navin Srivastava, Roberto Suaya, Kaustav Banerjee:
Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. DATE 2010: 459-464
2000 – 2009
- 2009
- [j4]Navin Srivastava, Roberto Suaya, Kaustav Banerjee:
Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(7): 1047-1060 (2009) - 2008
- [c9]Navin Srivastava, Roberto Suaya, Kaustav Banerjee:
High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. DATE 2008: 426-431 - 2007
- [c8]Salvador Ortiz, Roberto Suaya:
Efficient implementation of conduction modes for modelling skin effect. ISVLSI 2007: 500-505 - 2006
- [c7]Salvador Ortiz, Roberto Suaya:
Fullwave volumetric Maxwell solver using conduction modes. ICCAD 2006: 13-18 - [c6]Rafael Escovar, Salvador Ortiz, Roberto Suaya:
Mutual inductance between intentional inductors: closed form expressions. ISCAS 2006 - 2005
- [j3]Rafael Escovar, Salvador Ortiz, Roberto Suaya:
An improved long distance treatment for mutual inductance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 783-793 (2005) - [c5]Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen:
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? ASP-DAC 2005 - 2004
- [j2]Rafael Escovar, Roberto Suaya:
Optimal design of clock trees for multigigahertz applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3): 329-345 (2004) - [c4]Rafael Escovar, Salvador Ortiz, Roberto Suaya:
Mutual inductance extraction and the dipole approximation. ISPD 2004: 162-169 - 2002
- [c3]Rafael Escovar, Roberto Suaya:
Transmission line design of clock trees. ICCAD 2002: 334-340
1990 – 1999
- 1991
- [c2]Jeffrey Joyce, Erwin Liu, John M. Rushby, Natarajan Shankar, Roberto Suaya, Friedrich W. von Henke:
From formal verification to silicon compilation. Compcon 1991: 450-455 - [c1]Paul de Dood, John Wawrzynek, Erwin Liu, Roberto Suaya:
A Two-Dimensional Topological Compactor With Octagonal Geometry. DAC 1991: 727-731 - 1990
- [j1]John Valainis, Sinan Kaptanoglu, Erwin Liu, Roberto Suaya:
Two-dimensional IC layout compaction based on topological design rule checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 260-275 (1990)
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