default search action
ITC 1992: Baltimore, MD, USA
- Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992. IEEE Computer Society 1992, ISBN 0-7803-0760-7
Session 1: Plenary
Keynote Address
- Andrew Rappaport:
The Great ATE Robbery. ITC 1992: 18
Invited Address
- Ben Bennetts:
Progress in DFT: A Personal View. ITC 1992: 19-20
Session 2: Test Generation from Switch to Multiprocessor
- Uwe Gläser, Uwe Hübner, Heinrich Theodor Vierhaus:
Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects. 21-29 - Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy:
A Small Test Generator for Large Designs. 30-40 - Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi:
Sequential Test Generation Based on Real-Value Logic. 41-48 - Jaushin Lee, Janak H. Patel:
An Instruction Sequence Assembling Methodology for Testing Microprocessors. 49-58
Session 3: Test Architecture
- Jim Chapman:
High-Performance CMOS-Based VLSI Testers: Timing Control and Compensation. 59-67 - Akinori Maeda:
The Advanced Test System Architecture Provides Fast and Accurate Test for a High Resolution ADC. 68-75 - Matthew L. Fichtenbaum, Robert J. Muller:
A VXI Driver-Sensor Instrument with Large Tester Architecture. 76-83
Session 4: Boundary Scan: Device Level Applications
- Wayne T. Daniel:
Design Verification of a High Density Computer Using IEEE 1149.1. 84-90 - John Andrews:
IEEE 1149.1 Applied to Mixed TTL-ECL and Differential Logic. 91-95 - E. Kofi Vida-Torku:
Impact of Boundary Scan Design on Delay Test. 96-105 - Barry Caldwell, Tom Langford:
Is IEEE 1149.1 Boundary Scan Cost Effective: A Simple Case Study. 106-109
Session 5: New Approaches to BIST
- Jos van Sas, Francky Catthoor, Hugo De Man:
Optimized BIST Strategies for Programmable Data Paths Based on Cellular Automata. 110-119 - Sybille Hellebrand, Steffen Tarnick, Bernard Courtois, Janusz Rajski:
Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers. 120-129 - Albrecht P. Stroele:
Self-Test Scheduling with Bounded Test Execution. 130-139 - Sandeep K. Gupta, Dhiraj K. Pradhan:
Can Concurrent Checkers Help BIST? 140-150
Session 6: Should We Go Beyond Stuck-at Faults to Improve Quality?
- Roger Perry:
IDDQ Testing in CMOS Digital ASIC's - Putting it All Together. 151-157 - K. Sawada, S. Kayano:
An Evaluation of IDDQ Versus Conventional Testing for CMOS Sea-of-Gate IC's. 158-167 - Peter C. Maxwell, Robert C. Aitken, Vic Johansen, Inshen Chiang:
The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need? 168-177
Session 7: Testing and Diagnosis of Sequential Circuits
- Elizabeth M. Rudnick, W. Kent Fuchs, Janak H. Patel:
Diagnostic Fault Simulation of Sequential Circuits. 178-186 - Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
:
Sequential Circuit Diagnosis Based on Formal Verification Techniques. 187-196 - John Moondanos, Jacob A. Abraham:
Sequential Redundancy Identification Using Verification Techniques. 197-205
Session 8: Boundary Scan: System Level Design and Application
- Lee Whetsel:
A Proposed Method of Accessing 1149.1 in a Backplane Environment. 206-216 - José M. M. Ferreira, Filipe S. Pinto, José Silva Matos:
A Boundary Scan Test Controller for Hierarchical BIST. 217-223 - Stephen C. Hilla:
Boundary Scan Testing for Multichip Modules. 224-231
Session 9: New Test and Development Methods
- Frank Bouwman, Steven Oostdijk, Rudi Stans, Ben Bennetts, Frans P. M. Beenker:
Macro Testability: The Results of Production Device Applications. 232-241 - Haruo Kato:
CCD Image Sensor Test Using Cellular Automation-Type Pattern Recognition System. 242-246 - Ran Edeleman, Ishai Kreiser:
Correlation of Capacitive Load Delay. 247-252
Session 10 - Panel: MCM Testing: Bringing MCMs into the Mainstream
- David C. Keezer
MCM Test Using Available Technology. 253
Session 11 - Panel: The Agony of Short Time to Market
- Keith Baker:
Time-to-Market: An Issue in Mixed-signal vs. Analogue. 254
Session 12 - Panel: Does Object-Oriented Programming Fit in Real World ATE?
- Richard S. Levy:
Does Object-Oriented Programming Fit in the Real World of ATE? 255-256 - James R. Ward:
The Reality of Object Oriented Solutions for ATE. 257-258
Session 13 - Panel: Memory Testing Technology in a Gigabit Age in Japan
- T. Yamada, Akihiro Fujiwara, Michiko Inoue:
COM (Cost Oriented Memory) Testing. 259
Session 14: IC Manufacturer Practical Quality Improvement Techniques
- Robert Trahan, Rex Kiang:
An Analysis of the Die Testing Process Using Taguchi Techniques and Circuit Diagnostics. 260-269 - Robert James Montoya:
Using Tester Repeatability to Improve Yields. 270-274 - Sarkis Ourfalian:
Successful Implementation of SPC in Semiconductor Final Test. 275-282
Session 15: Scan Design: More Bang for Less Bucks
- Hideo Fujiwara, Akihiro Yamamoto:
Parity-Scan Design to Reduce the Cost of Test Application. 283-292 - Sridhar Narayanan, Charles Njinda, Melvin A. Breuer:
Optimal Sequencing of Scan Registers. 293-302 - Sungju Park, Sheldon B. Akers:
A Graph Theoretic Approach to Partial Scan Design by K-Cycle Elimination. 303-311
Session 16: Analog to Digital Converter Testing
- Shoba Krishnan, Sondes Sahli, Chin-Long Wey:
Test Generation and Concurrent Error Detection in Current-Mode A/D Converters. 312-320 - Masao Sugai, Takayuki Nakatani:
AC Dynamic Testing of 20Bit Sigma-Delta Over-Sampling D/A Converter on a Mixed Signal Test System. 321-327
Session 17: Board Test
- Frans G. M. de Jong, Adriaan J. de Lind van Wijngaarden
Memory Interconnection Test at Board Level. 328-337 - Shuichi Kameyama, Hideyuki Ohara, Chihiro Endo, Naoki Takayama:
Interconnect and Delay Testing with a 4800-Pin Board Tester. 338-344 - Gaspare Pantano, Dave Rolince:
VECTOR (Virtual Edge Connector Test): A Strategy to Increase TPS Fault Coverage Without Adding Test Vectors. 345-351
Session 18: Three Approaches to Increase Good Product Shipped
- Richard H. Williams, R. Glenn Wagner, Charles F. Hawkins:
Testing Errors: Data and Calculations in an IC Manufacturing Process. 352-361 - Babur Mustafa Pulat, Lauren M. Streb:
Position of Component Testing in Total Quality Management (TQM). 362-366 - Mick Tegethoff, T. E. Figal, S. W. Hird:
Board Test DFT Model for Computer Products. 367-371
Session 19: Boundary Scan: Board Level Design and Analysis
- Marcelo Lubaszewski, Bernard Courtois:
On the Design of Self-Checking Boundary Scannable Boards. 372-381 - Wei-Cheng Her, Lin-Ming Jin, Yacoub M. El-Ziq:
An ATPG Driver Selection Algorithm for Interconnect Test with Boundary Scan. 382-388 - Matthew Melton, Franc Brglez:
Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults. 389-398
Session 20: Error Modeling and Design for Test in Mixed Signal Devices
- Timothy Daniel Lyons:
The Production Implementation of a Linear Error Modeling Technique. 399-404 - Stephen C. Bateman, William H. Kao:
Simulation of an Integrated Design and Test Environment for Mixed-Signal Integrated Circuits. 405-414 - Alaa F. Alani, Gerry Musgrave, Anthony P. Ambler:
A Steady-State Response Test Generation for Mixed-Signal Integrated Circuits. 415-421
Session 21: ATE Timing Subsystems
- R. Warren Necoechea:
High Performance Monolithic Verniers for VLSI Automatic Test Equipment. 422-430 - Gary Fehr:
Timing-Per-Pin Flexibility at Shared-Resource Cost. 431-438 - Timothy Alton:
TGEN: Flexible Timing Generator Architecture. 439-443
Session 22: Test Data Management
- Christopher L. Henderson, Richard H. Williams, Charles F. Hawkins:
Economic Impact of Type I Test Errors at System and Board Levels. 444-452 - Michael G. Wahl, Carol Pyron:
EDIF Test - The Upcoming Standard for Test Data Transfers. 453-458 - Bas Verhelst, Richard Morren, Keith Baker:
Using EDIF for Transfer of Test Data: Practical Experience. 459-465
Session 23: Bridging and Other Faults in CMOS Circuits
- Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò:
Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital ICs. 466-475 - Peter Lidén, Peter Dahlgren, Jan Torin:
Transistor Fault Coverage for Self-Testing CMOS Checkers. 476-485 - Marcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò:
Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs. 486-495
Session 24: BIST Design Techniques
- Gordon R. Mc Leod:
BIST Techniques for ASIC Design. 496-505 - Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan:
ScanBIST: A Multi-frequency Scan-based BIST Method. 506-513 - Wei-Lun Wang, Jhing-Fa Wang, Kuen-Jong Lee:
A Fast Testing Method for Sequential Circuits at the State Trasition Level. 514-519
Session 25: ATE Timing Accuracy and Calibration
- Herbert Thaler, Lee Holt:
A Suite of Novel Digital ATE Timing Calibration Methods. 520-529 - David C. Keezer
Calibration Techniques for a Gigahertz Test System. 530-537 - Ulrich Schoettmer, Holger Engelhard:
High Performance Pin Electronics with GaAs, A Contradiction in Terms? 538-545
Session 26 - Panel: Systems Testing - The Home for All Product Test Planning?
- Maury A. Smeyne:
System Test: What is it? Why Bother Defining It? 546 - William R. Simpson, John W. Sheppard
System Perspective on Diagnostic Testing. 547 - Charles F. Hawkins:
System Testing: The Future for All of Us. 548
Session 27 - Panel: Is IC Burn-In or Burned-Out - Part 2
- Noel E. Donlin:
Is Burn-In Burned-Out - Part 2. 549-550
Session 28 - Panel: Software Testing: Opportunity and Nightmare
- Anneliese von Mayrhauser:
Software Testing: Opportunity and Nightmare. 551-552 - Simeon C. Ntafos:
Software Testing: Theory and Practice. 553
Session 29 - Panel: P1149.4 Mixed-Signal Test Bus Framework Proposals
- Richard Hulse:
A Mixed Signal Analog Test Bus Framework. 554 - Madhuri Jarwala:
Design for Test Approaches to Mixed-Signal Testing. 555 - Brian R. Wilkins:
A Structure for Board-Level Mixed-Signal Testability. 556-557
Session 30: System Issues in Delay Testing
- Bejoy G. Oomman, Prasad Kongara, Chittaranjan Mallipeddi:
Amdahl Corporation Board Delay Test System. 558-567 - Yaron Aizenbud, Paul Chang, Moshe Leibowitz, Dave Smith, Bernd Könemann, Vijay S. Iyengar, Barry K. Rosen:
AC Test Quality: Beyond Transition Fault Coverage. 568-577 - Bernd Könemann, J. Barlow, Paul Chang, R. Gabrielson, C. Goertz, Brion L. Keller, Kevin McCauley, J. Tischer, Vijay S. Iyengar, Barry K. Rosen, T. Williams:
Delay Test: The Next Frontier for LSSD Test Systems. 578-587 - Weiwei Mao, Michael D. Ciletti:
Robustness Enhancement and Detection Threshold Reduction in ATPG for Gate Delay Faults. 588-597
Session 31: Memory Design and Test Techniques
- Michael Nicolaidis:
Transparent BIST for RAMs. 598-607 - Hideshi Maeno, Koji Nii
LSSD Compatible and Concurrently Testable Ram. 608-614 - Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima:
A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. 615-622 - Tom Chen, Glen Sunada:
A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories. 623-631
Session 32: Advances in Design for Testability Techniques
- Xiaoqing Wen, Kozo Kinoshita:
Testable Designs of Sequential Circuits Under Highly Observable Condition. 632-641 - M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa
Physical DFT for High Coverage of Realistic Faults. 642-651 - Andrzej Krasniewski, Slawomir Pilarski:
High Quality Testing of Embedded RAMs Using Circular Self-Test Path. 652-661 - Miron Abramovici, Prashant S. Parikh:
Warning: 100% Fault Coverage May Be Misleading!! 662-668
Session 33: Microprocessor Testing Case Studies
- Paul Astrachan, Todd Brooks, Jody Everett, Wai-On Law, Kenneth McIntyre, Chuong Nguyen, Charles Weng:
Testing a DSP-Based Mixed-Signal Telecommunications Chip. 669-677 - J. Preißner, G.-H. Huaman-Bollo, G. Mahlich, Johannes Schuck, Hans Sahm, P. Weingart, D. Weinsziehr, J. Yeandel, R. Evans:
An Open Modular Test Concept for the DSP KISS-16Vs. 678-683 - Ad J. van de Goor, Th. J. W. Verhallen:
Functional Testing of Current Microprocessors (applied to the Intel i860TM). 684-695 - Marcus Rimén, Joakim Ohlsson:
A Study of the Error Behavior of a 32-bit RISC Subjected to Simulated Transient Fault Injection. 696-704
Session 34: Advanced Delay Testing
- Jacob Savir:
Skewed-Load Transition Test: Part 1, Calculus. 705-713 - Srinivas Patil, Jacob Savir:
Skewed-Load Transition Test: Part 2, Coverage. 714-722 - Kwang-Ting Cheng
Transition Fault Simulation for Sequential Circuits. 723-731
Session 35: Test Synthesis
- Oliver F. Haberl, Thomas Kropf:
HIST: A Methodology for the Automatic Insertion of a Hierarchical Self Test. 732-741 - Pi-Yu Chung, Ibrahim N. Hajj:
ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits. 742-751 - Vivek Chickermane, Jaushin Lee, Janak H. Patel:
Design for Testability Using Architectural Descriptions. 752-761
Session 36: CAE for Defect Detection and I-DDQ Testing
- Rohit Kapur, Jaehong Park, M. Ray Mercer:
All Tests for a Fault Are Not Equally Valuable for Defect Detection. 762-769 - Ravi K. Gulati, Weiwei Mao, Deepak K. Goel:
Detection of "Undetectable" Faults Using IDDQ Testing. 770-777 - Robert C. Aitken:
A Comparison of Defect Models for Fault Location with IDDQ Measurements. 778-787
Session 37: Special Topics in Mixed Signal Testing
- Eric Rosenfeld:
A Method of Jitter Measurement. 788-794 - Takashi Kido:
In-Process Inspection Technique for Active-Matrix LCD Panels. 795-799 - Paul Kelley:
Testing Video Processors. 800-806
Session 38: Test Generation Techniques
- Miron Abramovici, Mahesh A. Iyer
One-Pass Redundancy Identification and Removal. 807-815 - Wolfgang Kunz, Dhiraj K. Pradhan:
Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits. 816-825 - Bernd Könemann, Phil Noto:
A Test Generation Methodology for High-Performance Computer Chips and Modules. 826-833
Session 39: Contactless Probing
- Mitsuru Shinagawa, Tadao Nagatsuma:
An Automated Optical On-Wager Probing System for Ultra-High-Speed ICs. 834-839 - R. Scharf, Claus Kuntzsch, Klaus Helmreich, Werner Wolz, Klaus D. Müller-Glaser:
DRC-based Selection of Optimal Probing Points for Chip-Internal Measurements. 840-847 - Alan C. Noble:
IDA: A Tool for Computer-Aided Failure Analysis. 848-853
Session 40: Developments in CAD to Test
- R. Arnold, Michael Chowanetz, Werner Wolz, Klaus D. Müller-Glaser:
Test/Agent: CAD-integrated Automatic Generation of Test Programs. 854-859 - William Kao, Jean Xia, Tom Boydston:
Automatic Test Program Generation for Mixed Signal ICs via Design to Test Link. 860-865 - R. Mehtani, M. De Jonghe, Richard Morren, Keith Baker:
Improving Total IC Design Quality Using Application Mode Testing. 866-872
Session 41: Unique Design, Fault, and Defect Issues
- Yukiya Miura, Kozo Kinoshita:
Circuit Design for Built-in Current Testing. 873-881 - Siyad C. Ma, Edward J. McCluskey:
Non-Conventional Faults in BiCMOS Digital Circuits. 882-891 - Rosa Rodríguez-Montañés, Joan Figueras, Eric Bruls:
Bridging Defects Resistance Measurements in a CMOS Process. 892-899
Session 42: Testing Computer Software
- James M. Bieman, Hwei Yin:
Designing for Software Testability Using Automated Oracles. 900-907 - Anneliese von Mayrhauser, James Keables:
A Simulation Environment for Early Lifecycle Software Reliability Research and Prediction. 908-916 - Ilene Burnstein, Nitya Jani, Steve Mannina, Joe Tamsevicius, Michael Goldshteyn, Louis Lendi:
Intelligent Fault Localization in Software. 917-926
Session 43: High Performance Probing
- January Kister, Robert L. Franch:
Advances in Membrane Probe Technology. 927-935 - Eswar Subramanian, Randy Nelson:
Enhanced Probe Card Facilities At-Speed Wafer Probing in Very High Density Applications. 936-939 - Daniel T. Hamling:
A 3GHz, 144 Point Probe Fixture for Automatic IC Wafer Testing. 940-947
Session 44: Self-Checking, Concurrent Testing, and Self-repair
- Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò:
CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults. 948-957 - Xiaoling Sun, Micaela Serra:
Merging Concurrent Checking and Off-line BIST. 958-967 - Pinaki Mazumder:
An Integrated Built-In Self-Testing and Self-Repair of VLSI/WSI Hexagonal Arrays. 968-977
Session 45: System Testing
- Kevin T. Kornegay
An Architecture for a Reconfigurable IEEE 1149.n Master Controller Board. 978-983 - David L. Landis, Chuck Hudson, Patrick F. McHugh:
Applications of the IEEE P1149.5 Module Test and Maintenance Bus. 984-992 - Najmi T. Jarwala, Paul Stiling, Enn Tammaru, Chi W. Yau:
A Framework for Boundary-Scan Based System Test Diagnosis. 993-998
1991 Best Paper Award
- William C. Bruce, Michael G. Gallup, Grady Giles, Tom Munns:
Implementing 1149.1 on CMOS Microprocessors. 999-1006
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-15 19:20 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: