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John Moondanos
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2010 – 2019
- 2018
- [c14]Michael K. Tsiampas, Nestor E. Evmorfopoulos, Konstantis Daloukas, John Moondanos, Georgios I. Stamoulis:
A power-supply noise aware dynamic timing analysis methodology, based on a statistical prediction engine. DTIS 2018: 1-6 - 2010
- [c13]Nestoras E. Evmorfopoulos, Maria-Aikaterini Rammou, George I. Stamoulis, John Moondanos:
Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis. ICCAD 2010: 824-830
2000 – 2009
- 2007
- [c12]Feijun Zheng, Kwang-Ting Cheng, Xiaolang Yan, John Moondanos, Ziyad Hanna:
An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability. ATS 2007: 288-294 - 2006
- [c11]Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng
, John Moondanos, Ziyad Hanna:
Generation of shorter sequences for high resolution error diagnosis using sequential SAT. ASP-DAC 2006: 25-29 - [c10]John Moondanos:
From Error to Error: Logic Debugging in the Many-Core Era. V&D@FLoC 2006: 3-7 - 2005
- [c9]Abhijit Davare, Qi Zhu
JPEG Encoding on the Intel MXP5800: A Platform-Based Design Case Study. ESTIMedia 2005: 89-94 - 2004
- [j2]Feng Lu, Li-C. Wang, Kwang-Ting (Tim) Cheng, John Moondanos, Ziyad Hanna:
A Signal Correlation Guided Circuit-SAT Solver. J. Univers. Comput. Sci. 10(12): 1629-1654 (2004) - [c8]Maher N. Mneimneh, Karem A. Sakallah, John Moondanos:
Preserving synchronizing sequences of sequential circuits after retiming. ASP-DAC 2004: 579-584 - 2003
- [c7]Feng Lu, Li-C. Wang, Kwang-Ting Cheng
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. DAC 2003: 436-441 - 2002
- [c6]Zurab Khasidashvili, John Moondanos, Ziyad Hanna:
TRANS: efficient sequential verification of loop-free circuits. HLDVT 2002: 115-120 - 2001
- [c5]John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss:
CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. CAV 2001: 131-143 - [c4]Zurab Khasidashvili, John Moondanos, Daher Kaiss, Ziyad Hanna:
An enhanced cut-points algorithm in formal equivalence verification. HLDVT 2001: 171-176
1990 – 1999
- 1997
- [j1]Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos:
Automatic verification of implementations of large circuits against HDL specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(3): 217-228 (1997) - 1994
- [c3]Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell:
Abstraction of data path registers for multilevel verification of large circuits. Great Lakes Symposium on VLSI 1994: 11-14 - [c2]Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell:
Verification of Circuits Described in VHDL through Extraction of Design Intent. VLSI Design 1994: 417-420 - 1992
- [c1]John Moondanos, Jacob A. Abraham:
Sequential Redundancy Identification Using Verification Techniques. ITC 1992: 197-205
Coauthor Index
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