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Charles Njinda
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2000 – 2009
- 2004
- [c11]Charles Njinda:
A Hierarchical DFT Architecture for Chip, Board and System Test/Debug. ITC 2004: 1061-1071
1990 – 1999
- 1997
- [c10]Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh:
Efficient Testing of Clock Regenerator Circuits in Scan Designs. DAC 1997: 95-100 - [c9]Rajesh Raina, Charles Njinda, Robert F. Molyneaux:
How Seriously Do You Take Your Possible-Detect Faults? ITC 1997: 819-828 - 1995
- [c8]Charles Njinda, Neeraj Kaul:
Performance Driven BIST Technique for Random Logic. ITC 1995: 524-533 - 1994
- [j2]Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer:
SWiTEST: a switch level test generation system for CMOS combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5): 625-637 (1994) - [c7]Ishwar Parulkar, Melvin A. Breuer, Charles Njinda:
Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. DAC 1994: 345-356 - 1993
- [j1]Sen-Pin Lin, Charles Njinda, Melvin A. Breuer:
Generating a family of testable designs using the BILBO methodology. J. Electron. Test. 4(1): 71-89 (1993) - 1992
- [c6]Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer:
SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. DAC 1992: 26-29 - [c5]Sridhar Narayanan, Charles Njinda, Rajesh Gupta, Melvin A. Breuer:
SIESTA: a multi-facet scan design system. EURO-DAC 1992: 246-251 - [c4]Sridhar Narayanan, Charles Njinda, Melvin A. Breuer:
Optimal Sequencing of Scan Registers. ITC 1992: 293-302 - 1991
- [c3]Debaditya Mukherjee, Charles Njinda, Melvin A. Breuer:
Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware. ICCAD 1991: 236-239 - [c2]Sen-Pin Lin, Charles Njinda, Melvin A. Breuer:
A Systematic Approach for Designing Testable VLSI Circuits. ICCAD 1991: 496-499 - [c1]Rajagopalan Srinivasan, Charles Njinda, Melvin A. Breuer:
A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing. VTS 1991: 34-39
Coauthor Index
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