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CN106971993B - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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Publication number
CN106971993B
CN106971993B CN201710028178.0A CN201710028178A CN106971993B CN 106971993 B CN106971993 B CN 106971993B CN 201710028178 A CN201710028178 A CN 201710028178A CN 106971993 B CN106971993 B CN 106971993B
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China
Prior art keywords
substrate
layer
semiconductor chip
metal layer
metal
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CN201710028178.0A
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English (en)
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CN106971993A (zh
Inventor
金志澈
金载春
柳翰成
赵京淳
赵暎相
尹汝勋
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020160059712A external-priority patent/KR102595276B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN106971993A publication Critical patent/CN106971993A/zh
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Abstract

提供了一种半导体封装件，所述半导体封装件包括：再分布基底；互连基底，在再分布基底上；半导体芯片，在再分布基底上且在互连基底的孔中；金属层，在半导体芯片上；模制层，在半导体芯片和互连基底之间的间隙中。互连基底包括穿透其内部的孔。互连基底包括基础层和延伸穿过基础层的导电构件。互连基底的顶表面定位在金属层的顶表面的水平之上或之下的水平。

Description

半导体封装件
本专利申请要求于2016年1月14日提交的第62/278,523号美国临时专利申请的权益以及于2016年5月16日提交的韩国专利申请10-2016-0059712的优先权，该美国临时专利申请和韩国专利申请的全部内容通过引用包含于此。
技术领域
下面描述的在此所述主题的示例性实施例涉及一种半导体封装件，更具体地，涉及一种包括再分布基底的半导体封装件。
背景技术
提供半导体封装件以实现适合在电子设备中使用的集成电路芯片。典型地，在半导体封装件中，在印刷电路板(PCB)上安装半导体芯片，使用接合线或凸块将半导体芯片电连接到印刷电路板。随着需要更大集成度的电子产品的出现，导致安装在印刷电路板上的半导体芯片的更大密度，对于半导体芯片和印刷电路板的高性能、高速度和紧凑尺寸已经有相应的越来越多的需求。因此，半导体封装件具有与其所需的紧凑尺寸伴随的翘曲问题。
发明内容
下面公开的示例性实施例提供一种能够防止翘曲的半导体封装件。
下面描述的示例性实施例提供一种具有紧凑尺寸的半导体封装件。
根据示例性实施例，半导体封装件可以包括：再分布基底；互连基底，在再分布基底上，互连基底包括穿透其内部的孔；半导体芯片，在再分布基底上且在互连基底的孔中；金属层，在半导体芯片上；模制层，在半导体芯片和互连基底之间的间隙中。互连基底可以包括基础层和延伸穿过基础层的导电构件。互连基底的顶表面可以定位在比金属层的顶表面的水平低的水平。
互连基底可以在所有侧面上围绕半导体芯片，模制层可以在所有侧面上围绕半导体芯片并且在半导体芯片的顶表面上方延伸。模制层可以由诸如环氧树脂等的连续的均质材料形成。
根据示例性实施例，半导体封装件可以包括：基底；半导体芯片，在基底上；第一金属层，在半导体芯片上；互连基底，与半导体芯片并排设置在基底上，在平面图中围绕半导体芯片；模制层，在半导体芯片和互连基底之间的间隙中。互连基底可以包括基础层和延伸穿过基础层的导电构件。
根据示例性实施例，半导体封装件可以包括：再分布基底；互连基底，位于再分布基底上，互连基底包括穿透其内部的孔；半导体芯片，位于再分布基底上且位于互连基底的孔中；金属层，位于半导体芯片上；模制层，位于半导体芯片和互连基底之间的间隙中。互连基底包括基础层和延伸穿过基础层的导电构件。互连基底的顶表面定位在与金属层的顶表面平齐或者比金属层的顶表面的水平高的水平。
附图说明
图1A是示出根据示例性实施例的制造半导体封装件的方法的平面图。
图1B是示出根据示例性实施例的第一封装件的平面图。
图2A至图2F是示出根据示例性实施例的制造半导体封装件的方法的剖视图。
图2G是示出根据示例性实施例的半导体封装件的剖视图。
图3A是用来解释根据示例性实施例的制造金属层的方法的平面图。
图3B至图3D是示出制造金属层的方法的与沿图3A的线III-III′截取的剖视图对应的剖视图。
图4A是示出根据示例性实施例的第一封装件的平面图。
图4B和图4C是示出根据示例性实施例的制造第一封装件的方法的与沿图4A的线IV-IV′截取的剖视图对应的剖视图。
图5A是示出根据示例性实施例的第一封装件的剖视图。
图5B是示出根据示例性实施例的第一封装件的剖视图。
图5C是示出根据示例性实施例的第一封装件的剖视图。
图5D至图5E是分别示出根据示例性实施例的第一封装件的剖视图。
图6A至图6C是示出根据示例性实施例的制造半导体封装件的方法的剖视图。
图7A至图7D是示出根据示例性实施例的制造半导体封装件的方法的剖视图。
图8A至图8D是示出根据示例性实施例的制造半导体封装件的方法的剖视图。
图9A是示出根据示例性实施例的第一封装件的与沿图1B的线II-II′截取的剖视图对应的剖视图。
图9B是示出根据示例性实施例的半导体封装件的与沿图1B的线II-II′截取的剖视图对应的剖视图。
图10A是示出根据示例性实施例的半导体封装件的与沿图1B的线II-II′截取的剖视图对应的剖视图。
图10B是示出根据示例性实施例的半导体封装件的与沿图1B的线II-II′截取的剖视图对应的剖视图。
具体实施方式
图1A是示出根据示例性实施例的制造半导体封装件的方法的平面图。图1B是示出根据示例性实施例的第一封装件的平面图。图2A至图2F是示出根据示例性实施例的制造半导体封装件的方法的剖视图。图2A至图2E对应于沿图1A的线I-I′截取的剖视图，图2F至图2G对应于沿图1B的线II-II′截取的剖视图。
如图1A和图2A中所示，可以在载体基底100上设置互连基底200。可以通过载体胶层150将互连基底200粘附到载体基底100。互连基底200可以包括穿透其内部的孔290。互连基底200可以包括基础层210和延伸穿过基础层210的导电构件220。例如，印刷电路板(PCB)可以用作互连基底200。导电构件220可以包括下焊盘221、线图案222、过孔223和上焊盘224。下焊盘221可以设置在互连基底200的底表面200b上。过孔223可以穿透基础层210中的至少一个。线图案222可以置于基础层210之间并且连接到过孔223。上焊盘224可以设置在基础层210的顶表面上并连接到过孔223中的至少一个。上焊盘224可以通过线图案222和过孔223电连接到下焊盘221。上焊盘224可以在第三方向D3上不与下焊盘221对齐。在该说明书中，可以将第三方向D3定义为垂直于互连基底200的底表面200b，可以将第一方向D1和第二方向D2定义为平行于互连基底200的底表面200b。第一方向D1可以与第二方向D2交叉。
如图1A和图2B中所示，可以在载体基底100上设置第一半导体芯片300。可以在互连基底200的孔290中设置第一半导体芯片300。第一半导体芯片300可以包括设置在它的底表面300b上的第一芯片焊盘301。第一芯片焊盘301可以面向载体基底100。第一半导体芯片300可以包括硅。
可以在第一半导体芯片300上设置金属层ML。金属层ML可以包括铜或铝。金属层ML可以具有在从大约15μm至大约25μm的范围内的厚度T1。金属层ML可以具有相对高的模量。例如，金属层ML可以具有大约大于大约50GPa的模量，具体地，在从大约50GPa到大约200GPa的范围内的模量。模量可以是指杨氏模量。当将压力作用于物质时，物质的变形程度可以随着其杨氏模量的增大而减小。可以在第一半导体芯片300和金属层ML之间形成粘合层350，从而可以将金属层ML粘到第一半导体芯片300。在下文中，下面进一步详细地讨论金属层ML的形成。
图3A是用来解释根据示例性实施例的形成金属层的方法的平面图。图3B至图3D是示出形成金属层的方法的与沿图3A的线III-III′截取的剖视图对应的剖视图。
如图3A和图3B中所示，可以将半导体基底1300设置为包括第一半导体芯片300。可以在半导体基底1300中设置多个第一半导体芯片300。半导体基底1300可以是由诸如硅的半导体形成的晶片级基底。第一半导体芯片300可以包括第一芯片焊盘301。
如图3A和图3C中所示，金属层ML可以设置在半导体基底1300上并且覆盖第一半导体芯片300的顶表面。金属层ML可以示出为具有与半导体基底1300的平面形状不同的平面形状，但是本示例性实施例不限于此。可以在第一半导体芯片300和金属层ML之间形成粘合层350。粘合层350可以是热固性聚合物或热塑性聚合物。例如，可以将粘合层350加热到大于大约150℃(具体地，在从大约150℃至大约250℃的范围内)，然后冷却到室温(例如，大约0℃至大约50℃)。通过加热和冷却，可以使粘合层350塑性变形而固化。可选择地，不形成粘合层350的情况下，可以在第一半导体芯片300上形成晶种层(未示出)。晶种层可以包括钛。可以通过溅射工艺或镀覆工艺在晶种层上形成金属层ML。在特定的实施例中，可以通过喷涂工艺(具体地，冷喷涂工艺)形成金属层ML。在这种情况下，可以不形成粘合层350和晶种层，而且金属层ML可以与第一半导体芯片300物理直接接触。
如图3A和图3D中所示，可以锯切金属层ML和半导体基底1300，使得第一半导体芯片300可以彼此分开。在锯切之后，每个第一半导体芯片300可以具有与设置在每个第一半导体芯片300的顶表面上的金属层ML的宽度W2基本上相同的宽度W1。在下文中将讨论第一半导体芯片300中单独的一个。
如图2B和图3C中所示，可以在载体基底100上设置其上设置有金属层ML的第一半导体芯片300。第一半导体芯片300可以面向载体基底100。可以在载体基底100上基本上同时设置第一半导体芯片300以及在其顶表面上的金属层ML。然而，不限于图3A至图3C中解释的示例性实施例，可以以各种方式改变第一半导体芯片300和金属层ML的形成步骤。例如，可以预先在载体基底100上设置第一半导体芯片300，然后可以在第一半导体芯片300上设置金属层ML。在这种情况下，金属层ML的宽度W2可以与对应的第一半导体芯片300的宽度W1基本上相同或不同。可选择地，在布置图2A中示出的互连基底200之前，可以执行图2B中示出的第一半导体芯片300的布置。在这种情况下，可以在载体基底100上设置第一半导体芯片300，并且可以在载体基底100上设置互连基底200，从而使孔290与第一半导体芯片300对齐。
如图1A和图2C中所示，可以在载体基底100上形成第一模制层400。第一模制层400可以覆盖互连基底200的顶表面和金属层ML的顶表面。第一模制层400可以设置在互连基底200和金属层ML之间的间隙中以及互连基底200和第一半导体芯片300之间的间隙中。第一模制层400可以包括绝缘聚合物，例如，环氧树脂类聚合物。可以在第一模制层400中形成开口401，从而可以暴露上焊盘224。可选择地，可以不形成开口401。如虚线所示，可以去除载体基底100和载体胶层150以暴露第一半导体芯片300的底表面300b以及互连基底200的底表面200b。
如图1A和图2D中所示，可以在第一半导体芯片300的底表面300b上和互连基底200的底表面200b上形成绝缘图案510和导电图案520，从而制造第一基底500。第一基底500可以是再分布基底。导电图案520可以包括设置在绝缘图案510之间的导电层和穿透绝缘图案510的过孔。导电图案520可以连接到第一半导体芯片300的第一芯片焊盘301以及互连基底200的下焊盘221。可以在第一基底500的底表面上形成保护层511。例如，保护层511可以包括与第一模制层400的材料相同的材料。然而，保护层511的材料不限于此。由于第一基底500被用作再分布基底，所以第一基底500可以具有比印刷电路板(即，互连基底200)的厚度小的厚度T2。例如，第一基底500具有小于大约0.01mm(优选地，小于大约0.02mm)的厚度T2。因此会能够减小半导体封装件的尺寸。
外部端子550可以设置在第一基底500的底表面上并且连接到导电图案520。外部端子550可以在第三方向D3上不与上焊盘224对齐。外部端子550的数目可以与上焊盘224的数目不同。外部端子550可以通过导电图案520、下焊盘221、线图案222和过孔223电连接到上焊盘224。可以在互连基底200中设置线图案222，从而上焊盘224在第三方向D3上可以不与下焊盘221对齐。导电图案520因此可以在数目和布置上少于上焊盘224或下焊盘221。因此，由于互连基底200的上焊盘224或下焊盘221使得导电图案520会在数目和布置上减少。可以进一步减小第一基底500的厚度T2。
导电图案520可以具有大于第一半导体芯片300的热膨胀系数(CTE)的CTE。例如，导电图案520可以具有大约25ppm/℃的CTE，第一半导体芯片300可以具有大约3ppm/℃的CTE。半导体封装件会遭受由导电图案520和第一半导体芯片300之间的CTE失配导致的翘曲。在一些示例性实施例中，金属层ML可以具有比第一半导体芯片300的CTE大并与导电图案520的CTE相似的CTE。例如，金属层ML可以具有在从大约25ppm/℃至大约50ppm/℃范围内的CTE。金属层ML可以横跨第一半导体芯片300面向导电图案520。第一半导体芯片300和金属层ML之间的CTE失配可以与第一半导体芯片300和金属层ML之间的CTE失配平衡。因此能够防止半导体封装件翘曲。在一些示例性实施例中，由于金属层ML具有较高的模量(例如，大于大约50GPa)，所以可以更加有利于防止半导体封装件翘曲。在金属层ML具有小于大约25ppm/℃的CTE、小于大约50Gpa的模量或小于大约15μm的小厚度的情况下，金属层ML会难以防止半导体封装件翘曲。可选择地，在金属层ML具有大于大约50ppm/℃的CTE或大于大约15μm的大厚度的情况下，金属层ML和第一半导体芯片300之间的CTE失配会变得过度地大。在这种情况下，半导体封装件会遭受由金属层ML和第一半导体芯片300之间的CTE失配引起的翘曲。
在一些示例性实施例中，如图2B中讨论的方法，可以将粘合层350硬化或塑性变形固化。粘合层350可以有助于防止半导体封装件翘曲。
金属层ML可以具有比第一半导体芯片300的热导率大的热导率。例如，金属层ML可以具有大于大约140W/mK(更具体地，在从大约140W/mK至大约300W/mK的范围内)的热导率。金属层ML可以具有大于第一半导体芯片300的热膨胀系数的热膨胀系数。当使用半导体封装件时，从第一半导体芯片300产生的热量可以通过金属层ML迅速地从封装件消散。因此会能够增强半导体封装件的操作可靠性。在粘合层350可以具有大于大约5μm的厚度的情况下，从第一半导体芯片300产生的热量可以相对缓慢地移至金属层ML。在一些示例性实施例中，粘合层350可以具有在从大约0.01μm至大约5μm的范围内的厚度T3。
如图1A、图1B和图2E中所示，可以锯切第一基底500和互连基底200以形成第一封装件P100。第一封装件P100中的每个可以与图1B中所示出的基本上相同。第一封装件P100的互连基底200可以包括孔290。
如图1B和图2F中所示，可以在图2E的第一封装件P100上安装第二封装件P200，从而可以制造半导体封装件1。第二封装件P200可以包括第二基底700、第二半导体芯片800和第二模制层900。第二半导体芯片800可以以倒装芯片方式安装在第二基底700上。与前面图中所示的不同，可以通过接合线(未示出)将第二半导体芯片800电连接到第二基底700。可以在第二基底700上设置第二模制层900以便覆盖第二半导体芯片800。可以在第二基底700的底表面上设置互连端子690。互连端子690可以连接到上焊盘224，使得第二封装件P200可以电连接到第一封装件P100。
图2G是示出根据示例性实施例的半导体封装件的剖视图。下面的描述中可以省略对上述相同或相似组件的重复描述。
如图2G中所示，半导体封装件2可以包括堆叠的第一封装件P100、第三封装件P300和第二封装件P200。可以通过与图1A至图2E中描述的方法相同的方法制造第一封装件P100。可以通过与图1A至图2E中讨论的在制造第一封装件P100的过程中描述的方法相同的方法制造第三封装件P300。例如，第三基底500′、第三半导体芯片300′、上粘合层350′、上互连基底200′、第三模制层400′和金属层ML′可以分别与第一基底500、第一半导体芯片300、粘合层350、互连基底200、第一模制层400和金属层ML基本上相同。上基础层210′和上导电构件220′可以分别与图2A的基础层210和导电构件220基本上相同。可以在第一封装件P100和第三封装件P300之间设置第一互连端子691。第一互连端子691可以连接到上焊盘224和导电图案520′。虽然示出了单个第三封装P300设置在第一封装P100上，但是可选择地，可以设置多个第三封装件P300。
可以在第三封装件P300上设置第二封装件P200。第二封装件P200可以包括第二基底700、第二半导体芯片800和第二模制层900。可以在第二封装件P200和第三封装件P300之间设置第二互连端子692。通过第二互连端子692可以将第二封装件P200电连接到第三封装件P300。
图4A是示出根据示例性实施例的第一封装件的平面图。图4B和图4C是示出根据示例性实施例的制造第一封装件的方法的与沿图4A的线IV-IV′截取的剖视图对应的剖视图。为了描述的简洁，在下文中将示出和讨论制造单个第一封装件的方法。然而，下面的示例性实施例不排除制造晶片级第一封装件的方法。如在先前所描述的示例性实施例中，在下面的描述中可以省略对上述相同或相似组件的重复描述。
如图4A和图4B中所示，可以在载体基底100上设置互连基底201和第一半导体芯片300。如图4A中所示，互连基底201可以具有矩形形状。可以设置多个互连基底201。如图4A中所示，多个互连基底201可以设置为围绕第一半导体芯片300。如图4B中所示，互连基底201中的每个可以包括基础层210和导电构件220。导电构件220可以包括下焊盘221、过孔223和上焊盘224。与图2A的互连基底200不同，可以省略线图案(由图2A的附图标记222指定)，过孔223可以与下焊盘221和上焊盘224直接接触。过孔223可以穿透基础层210。可以在设置第一半导体芯片300之前或之后将互连基底201设置在载体基底100上。可以通过粘合层350将金属层ML粘附到第一半导体芯片300。第一半导体芯片300、粘合层350和金属层ML可以与图3A至图3D中所讨论的基本上相同。可以在第一半导体芯片300和金属层ML之间的间隙中形成第一模制层400。可以去除载体基底100和载体胶层150以暴露第一半导体芯片300的底表面300b以及互连基底201的底表面201b。
如图4A和图4C中所示，可以在第一半导体芯片300的底表面300b上和互连基底201的底表面201b上形成第一基底500，从而制造第一封装件P101。第一基底500可以包括绝缘图案510和导电图案520。外部端子550可以形成在第一基底500的底表面上并且连接到导电图案520。可以将上面讨论的并在图2D中示出的相似或相同的组件应用于此处图4C中示出的第一基底500和外部端子550的形成方法和电连接。
图5A是示出根据示例性实施例的第一封装件的剖视图。在下面的描述中可以省略对上述相同或相似组件的重复描述。
如图5A中所示，第一封装件P102可以包括第一基底500、第一半导体芯片300、互连基底200、粘合层350和第一模制层400。可以将上面讨论的并在图1A至图2E中示出的相似或相同的组件基本上同等地应用于形成图5A中示出的第一基底500、第一半导体芯片300和互连基底200。上碳层360可以设置在金属层ML的顶表面上。上碳层360可以包括碳纳米管、石墨烯或石墨。例如，上碳层360可以直接生长在金属层ML的顶表面上，金属层ML可以设置在第一半导体芯片300上。在这种情况下，上碳层360可以具有与金属层ML的宽度和平面形状基本上相同的宽度和平面形状。可选择地，上碳层360可以预先在母板(未示出)上生长，然后设置在金属层ML上。上碳层360可以具有比第一半导体芯片300的热导率大的热导率。因此，当操作第一封装件P102时，可以通过金属层ML和上碳层360迅速地消散从第一半导体芯片300产生的热量。下碳层(未示出)可以进一步置于第一半导体芯片300和粘合层350之间。
第一模制层400可以覆盖互连基底200的顶表面和上碳层360的顶表面。第一模制层400可以具有暴露上焊盘224的开口401，如图2D和图5A中所示，第一模制层400可以与金属层ML的顶表面平齐或者在金属层ML的顶表面上方延伸。可选择地，第一模制层400可以不具有开口401。第一模制层400可以延伸到第一半导体芯片300与互连基底200的内表面200c之间的间隙中。第一模制层400可以不覆盖互连基底200的外表面200d。互连基底200的外表面200d可以面向互连基底200的内表面200c。
图5B是示出根据示例性实施例的第一封装件的剖视图。可以从下面的描述中省略对上述相同或相似组件的重复描述。
如图5B中所示，第一封装件P103可以包括第一基底500、第一半导体芯片300、互连基底200、粘合层350和第一模制层400。第一半导体芯片300可以包括在它内部的热源(未示出)。热源可以是诸如中央处理单元(CPU)、存储接口、通用串行总线(USB)等的IP块。IP块可以是指被配置为硬件或软件并且具有构成半导体集成电路所必需的功能的块。热点370可以由当操作第一半导体芯片300时产生超过特定量热的热的热源之一限定。
凹进380可以设置在第一半导体芯片300的顶表面上。金属层ML可以包括延伸到凹进380中的突起MLP。例如，凹进380、金属层ML和突起MLP可以形成在图3A和图3B的晶片级第一半导体芯片300上。可以使用其上设置有金属层ML的第一半导体芯片300制造第一封装件P103。突起MLP可以设置为与热点370相邻。例如，突起MLP可以在第三方向D3上与热点370对齐。不限于此处的图中所示出的，可以以各种方式改变突起MLP的剖面形状和数目。由于金属层ML具有突起MLP，所以可以在金属层ML和热点370之间达到小的距离。当操作第一半导体芯片300时，从热点370产生的热量可以通过突起MLP迅速地传递到金属层ML。因此突起MLP可以有利于增强第一半导体芯片300的操作可靠性。粘合层350可以置于金属层ML和第一半导体芯片300之间以及突起MLP和第一半导体芯片300之间。可选择地，可以省略粘合层350。
图5C是示出根据示例性实施例的第一封装件的剖视图。从接下来的描述中可以省略对上述相同或相似组件的重复描述。
如图5C中所示，第一封装件P104可以包括第一基底500、第一下半导体芯片310、第一上半导体芯片320、互连基底200、第一模制层400、粘合层350和金属层ML。
第一下半导体芯片310和第一上半导体芯片320可以包括与之前描述的第一半导体芯片300的材料基本上相同的材料。第一下半导体芯片310和第一上半导体芯片320可以在第一基底500上设置在互连基底200的孔290中。第一下芯片焊盘311可以设置在第一下半导体芯片310的底表面上并且连接到导电图案520。第一下半导体芯片310可以包括穿透其内部并且连接到第一下芯片焊盘311的通孔312。第一上半导体芯片320可以堆叠在第一下半导体芯片310上。第一上半导体芯片320可以包括在其底表面上的第一上芯片焊盘321。第一上芯片焊盘321可以连接到通孔312，使得第一上半导体芯片320可以电连接到第一基底500。
金属层ML可以设置在第一上半导体芯片320上。金属层ML可以具有比第一半导体芯片310和320的热导率和CTE大的热导率和CTE。金属层ML可以减小或防止第一封装件P104的翘曲。
图5D至图5E是分别示出根据本发明构思的示例性实施例的第一封装件的剖视图。
如图5D和图5E中所示，第一封装件P105和P106中的每个可以包括第一基底500、第一半导体芯片300、互连基底200、第一模制层400、粘合层350和金属层ML。可以将上面描述的并在图1A至图2E中示出的组件基本上同等地应用于下面描述中的第一基底500、第一模制层400、粘合层350、互连基底200和金属层ML。可以在互连基底200的孔290中设置多个第一半导体芯片300。第一半导体芯片300可以在第一方向D1上彼此分隔开。
如图5D中所示，金属层ML可以设置为单个连续的形成件并覆盖第一半导体芯片300。金属层ML的宽度W2可以与第一半导体芯片300的宽度W1的总和基本上相同或大于第一半导体芯片300的宽度W1的总和。
如图5E中所示，金属层ML可以以多个形成件设置。金属层ML可以分别设置在第一半导体芯片300上。金属层ML中的每个可以具有与第一半导体芯片300的其与金属层ML对应的一个第一半导体芯片的宽度W1基本上相同的宽度W2。
图6A至图6C是示出根据示例性实施例的制造半导体封装件的方法的剖视图。可以从下面的描述中省略对上述相同或相似组件的重复描述。
如图6A中所示，可以在载体基底100上设置第一半导体芯片300、互连基底200、第一模制层400和金属层ML。导电构件220可以包括接地图案220G和信号图案220S。接地图案220G可以包括下接地焊盘221G、接地线图案222G、接地过孔223G和上接地焊盘224G。信号图案220S可以包括下信号焊盘221S、信号线图案222S、信号过孔223S和上信号焊盘224S。信号图案220S可以与接地图案220G绝缘。下焊盘221G和221S可以设置在互连基底200的底表面200b上，上焊盘224G和224S可以设置在互连基底200的顶表面上。线图案222G和222S可以置于基础层210之间。过孔223G和223S可以穿透基础层210中的至少一个。
第一半导体芯片300可以包括第一接地芯片焊盘301G和第一信号芯片焊盘301S。第一接地芯片焊盘301G可以与第一信号芯片焊盘301S绝缘。第一模制层400可以设置在互连基底200的顶表面上和第一半导体芯片300的侧表面上，并且可以不覆盖第一半导体芯片300的顶表面以及上焊盘224G和224S的顶表面。
可以在第一半导体芯片300的顶表面上设置金属层ML。金属层ML可以具有与图2B中讨论的厚度和模量相同的厚度和模量，并且具有图2D中讨论的CTE和热导率。金属层ML的宽度W2可以大于第一半导体芯片300的宽度W1。金属层ML可以延伸到上接地焊盘224G中的一个上并且连接到上接地焊盘224G中的一个。金属层ML可以不覆盖上接地焊盘224G中的另外一个。金属层ML可以在第一方向D1上与上信号焊盘224S分隔开并且与上信号焊盘224S绝缘。此后，可以去除载体基底100和载体胶层150。
如图6B中所示，可以在第一半导体芯片300和互连基底200的底表面上形成第一基底500，从而制造第一封装件P107。第一基底500可以包括绝缘图案510、接地导电图案520G和信号导电图案520S。可以通过与在制造图2D的导电图案520的过程中描述的方法相同的方法形成导电图案520G和520S。接地导电图案520G可以连接到第一接地芯片焊盘301G和下接地焊盘221G。信号导电图案520S可以连接到第一信号芯片焊盘301S和下信号焊盘221S。信号导电图案520S可以与接地导电图案520G绝缘。
外部端子550G和550S分别描述外部接地端子和外部信号端子，并且可以形成在第一基底500的底表面上。可以将上面描述的并在图2D中示出的内容基本上同等地应用于外部端子550G和550S的形成和布置。接地端子550G和信号端子550S可以分别连接到接地导电图案520G和信号导电图案520S。金属层ML可以通过接地图案220G、接地导电图案520G和接地端子550G接地。可选择地，在形成第一基底500之后，可以在第一半导体芯片300上设置金属层ML。
如图6C中所示，可以准备第二封装件P200包括第二基底700、第二半导体芯片800和第二模制层900。第二半导体芯片800可以包括第二接地芯片焊盘801G和第二信号芯片焊盘801S。第二基底700可以包括上接地图案720G和上信号图案720S。上接地图案720G和上信号图案720S可以分别连接到第二接地芯片焊盘801G和第二信号芯片焊盘801S。接地互连端子690G和信号互连端子690S可以设置在第二基底700的底表面上，并且分别连接到上接地图案720G和上信号图案720S。
可以在图6B的第一封装件P107上设置第二封装件P200。这里，信号互连端子690S可以与第一封装件P107的上信号焊盘224S对齐。接地互连端子690G可以与通过金属层ML暴露的上接地焊盘224G中的一个对齐。可以执行焊接将信号互连端子690S连接到上信号焊盘224S。接地互连端子690G可以连接到通过金属层ML暴露的上接地焊盘224G中的一个。可以通过前述工艺制造半导体封装件3。
图7A至图7D是示出根据示例性实施例的制造半导体封装件的方法的剖视图。在下面的描述中可以省略对上述相同或相似组件的重复描述。
如图7A中所示，可以设置第一基底500、第一半导体芯片300、互连基底200和第一模制层400。可以将上面描述的并在图1A至图2E中示出的组件基本上同等地应用于形成在此描述的第一基底500、第一半导体芯片300、互连基底200和第一模制层400。另一方面，可以将第一半导体芯片300的顶表面300a定位在与互连基底200的顶表面200a的水平基本上相同的水平。导电构件220可以包括接地图案220G和信号图案220S。导电构件220和第一基底500之间的电连接可以与图6A中讨论的电连接基本上相同。为了描述的简洁，将在下文中讨论多个上信号焊盘224S和单个上接地焊盘224G，但是上信号焊盘224S和上接地焊盘224G的数目不限于此。
如图7B中所示，可以准备中间层600包括绝缘层610、金属层ML1和ML2、金属图案620以及金属过孔630G和630S。绝缘层610可以包括聚合物。例如，可以将柔性膜用作绝缘层610。绝缘层610可以具有彼此面向的第一表面610a和第二表面620a。可以在中间层600中设置金属层ML1和ML2。金属层ML1和ML2可以设置在绝缘层610的第二表面610b上。第一金属层ML1可以在第一方向D1上与第二金属层ML2分隔开，第一金属层ML1和第二金属层ML2可以彼此绝缘。第一金属层ML1和第二金属层ML2可以具有与前面描述的金属层ML的厚度、模量、CTE和热导率基本上相同的厚度、模量、CTE和热导率。可以在绝缘层610的第二表面610b上设置金属图案620。金属图案620可以在第一方向D1上与金属层ML1和ML2分隔开并且与金属层ML1和ML2绝缘。例如，可以通过与形成金属层ML1和ML2的方法相同的方法形成金属图案620。金属图案620因此可以包括与金属层ML1和ML2的材料和厚度基本上相同的材料和厚度。
可以在绝缘层610中设置金属过孔630G和630S。金属过孔630G和630S可以具有通过绝缘层610暴露的顶表面。金属接地过孔630G可以设置在第一金属层ML1上并连接到第一金属层ML1。金属信号过孔630S可以设置多个。金属信号过孔630S可以分别设置在第二金属层ML2和金属图案620上并且连接到第二金属层ML2和金属图案620。
如图7C中所示，图7B的中间层600可以设置在图7A的互连基底200和第一半导体芯片300上。在这一布置中，绝缘层610的第二表面610b可以面向第一半导体芯片300的顶表面。第一金属层ML1和第二金属层ML2可以覆盖第一半导体芯片300。第一金属层ML1可以延伸到上接地焊盘224G上并连接到上接地焊盘224G。第二金属层ML2可以延伸到第一半导体芯片300的上信号焊盘224S中的一个上并连接到第一半导体芯片300上的上信号焊盘224S中的所述一个。金属图案620可以连接到上信号焊盘224G中的另一个。可以在第一半导体芯片300与金属层ML1和ML2之间插入粘合层350。由此可以制造第一封装件P108。
如图7D中所示，可以在图7C的第一封装件P108上安装第二封装件P200，从而可以制造半导体封装件4。如图6C中讨论的，第二半导体芯片800可以电连接到第二基底700。第二接地芯片焊盘801G和第二信号芯片焊盘801S可以分别连接到上接地图案720G和上信号图案720S。可以在第二基底700的底表面上设置接地互连端子690G和信号互连端子690S。可以设置多个接地互连端子690G和多个信号互连端子690S。接地互连端子690G和信号互连端子690S可以分别连接到金属接地过孔630G和金属信号过孔630S。从第二半导体芯片800产生的或者传输到第二半导体芯片800的电信号可以通过金属图案620或第二金属层ML2传递到信号图案220S。互连端子690G和690S可以在数量、间距或布置方面与上焊盘224G和224S不同。可以设置中间层600，从而可以增加第二导电图案720G和720S的可能布置的数量。
图8A至图8D是示出根据示例性实施例的制造半导体封装件的方法的剖视图。可以从下面的描述中省略对上述相同或相似组件的重复描述。
如图8A中所示，可以设置第一基底500、第一半导体芯片300、互连基底200和第一模制层400。第一基底500、第一半导体芯片300、互连基底200和第一模制层400可以与图7A中讨论的第一基底500、第一半导体芯片300、互连基底200和第一模制层400基本上相同。
如图8B中所示，可以准备中间层600包括绝缘层610、金属层ML、金属图案620G和620S以及金属过孔631G、632G和630S。可以在中间层600中设置金属层ML。例如，可以在绝缘层610的第二表面610b上设置金属层ML。可以在绝缘层610的第一表面610a上设置金属图案620G和620S。金属接地图案620G可以与金属信号图案620S绝缘。
可以在绝缘层610中设置第一金属接地过孔631G、第二金属接地过孔632G和金属信号过孔630S。第一金属接地过孔631G可以置于金属层ML和金属接地图案620G之间并且连接到金属层ML和金属接地图案620G。第二金属接地过孔632G可以设置在接地图案620G上并且在第一方向D1上与金属层ML分隔开。第二金属接地过孔632G可以具有通过绝缘层610暴露的表面。金属信号过孔630S可以具有通过绝缘层610暴露的表面。
如图8C中所示，可以将图8B的中间层600设置在图8A的第一半导体芯片300和互连基底200上。在这一步骤中，绝缘层610的第二表面610b可以设置为面向第一半导体芯片300，因此金属层ML可以设置在第一半导体芯片300上。第二金属接地过孔632G和金属信号过孔630S可以分别连接到上接地焊盘224G和上信号焊盘224S。金属层ML可以通过第一金属接地过孔631G、金属接地图案620G、第二金属接地过孔632G、接地图案220G、接地导电图案520G和接地端子550G接地。由此可以制造第一封装件P109。
如图8D中所示，可以在图8C的第一封装件P109上安装第二封装件P200，从而可以制造半导体封装件6。第二半导体芯片800和第二基底700之间的电连接可以与图7D中讨论的第二半导体芯片800和第二基底700之间的电连接基本上相同。可以在第二封装件P200和中间层600之间形成互连端子690G和690S。接地互连端子690G和信号互连端子690S可以分别连接到金属接地图案620G和金属信号图案620S。第二封装件P200因此可以通过中间层600电连接到第一封装件P109。
图9A是示出根据示例性实施例的第一封装件P110的沿图1B的线II-II′截取的剖视图。在下面的描述中可以省略对上述相同或相似组件的重复描述。
如图9A和图1B中所示，第一封装件P110可以包括第一基底500、第一半导体芯片300、互连基底200和第一模制层400。
互连基底200可以具有比第一半导体芯片300的高度H2低的高度H1。互连基底200的顶表面200a可以定位在比第一半导体芯片300的顶表面300a的水平低的水平。
图9B是示出根据示例性实施例的半导体封装件的沿图1B的线II-II′截取的剖视图。在下面的描述中可以省略对上述相同或相似组件的重复描述。
如图9B和图1B中所示，半导体封装件7可以包括安装在图9A的第一封装件P110上的第二封装件P201。第二封装件P201可以包括第二基底700、第二半导体芯片800和第二模制层900。第二半导体芯片800可以通过接合线810电连接到第二基底700。可以设置多个第二半导体芯片800(未示出)。可以在上焊盘224和第二基底700之间设置互连端子690。可以将互连端子690连接到上焊盘224，从而可以将第二封装件P201电连接到第一封装件P110。
由于互连基底200具有相对小的高度H1，所以可以靠近于第一半导体芯片300上的第一模制层400设置第二基底700。例如，第二基底700可以与第一半导体芯片300上的第一模制层400分隔开小于大约30μm的间隔D。因此，半导体封装件7可以是紧凑或小尺寸的。
图10A是示出根据示例性实施例的半导体封装件的沿图1B的线II-II′截取的剖视图。可以从下面的描述中省略对上述相同或相似组件的重复描述。
如图10A和图1B中所示，半导体封装件8可以包括第一封装件P111和第二封装件P201。除了包括第一基底500、第一半导体芯片300、互连基底200和第一模制层400之外，第一封装件P111还可以包括粘合层350和金属层ML。可以在第一半导体芯片300上设置粘合层350和金属层ML。金属层ML可以防止或减小第一封装件P111的翘曲。从第一半导体芯片300产生的热量可以通过金属层ML迅速地消散到外部。可选择地，可以省略粘合层350。
互连基底200的高度H1可以相对地小。例如，互连基底200的高度H1可以小于第一半导体芯片300的高度H2和金属层ML的高度H3的总和。互连基底200的顶表面200a可以定位在比金属层ML的顶表面MLa的水平低的水平。因此，第二基底700和第一模制层400之间的间隔D可以小于大约30μm。半导体封装件8可以是紧凑或小尺寸的。
图10B是示出根据示例性实施例的半导体封装件的沿图1B的线II-II′截取的剖视图。可以从下面的描述中省略对上述相同或相似组件的重复描述。
如图10B和图1B中所示，半导体封装件9可以包括第一封装件P111和第二封装件P201。可以以与图10A中讨论的方式相同的方式设置第一半导体芯片300、互连基底200、粘合层350和金属层ML。
由于互连基底200具有相对小的高度H1，所以第一半导体芯片300上的第一模制层400可以具有物理地接触第二基底700的底表面700b的顶表面400a。半导体封装件9因此可以是紧凑或小尺寸的。当操作半导体封装件9时，第一半导体芯片300会产生热量。第一半导体芯片300、第一模制层400、粘合层350、金属层ML和第二封装件P201可以具有比空气的热导率大的热导率。第一模制层400可以与第二基底700物理接触，使得从第一半导体芯片300产生的热量可以迅速地传递到第二封装件P201。
根据示例性实施例，可以在半导体芯片的顶表面上设置金属层，从而会能够防止半导体芯片翘曲。可以将再分布图案用作基底，由此半导体封装件可以变为紧凑型。
虽然已经结合附图中示出的示例性实施例描述了本发明，但是本发明不限于此。对于本领域技术人员将明显的是，在不脱离在权利要求中阐述的本发明的范围和精神的情况下，可以对其做出各种替换、修改和改变。

Claims (19)

1.一种半导体封装件，所述半导体封装件包括：
再分布基底；
互连基底，位于再分布基底上，互连基底包括穿透其内部的孔；
半导体芯片，位于再分布基底上且位于互连基底的孔中；
金属层，位于半导体芯片上；以及
模制层，位于半导体芯片和互连基底之间的间隙中，
其中，互连基底包括基础层和延伸穿过基础层的导电构件，
其中，互连基底的顶表面定位在比金属层的顶表面的水平低的水平，
其中，模制层覆盖互连基底的顶表面和金属层的顶表面，
其中，金属层具有与半导体芯片的宽度和平面形状基本相同的宽度和平面形状，
其中，导电构件包括：下焊盘，位于互连基底的底表面上；线图案，位于基础层之间；过孔，穿透基础层；以及上焊盘，位于基础层的顶表面上，上焊盘通过过孔和线图案连接到下焊盘，并且
其中，上焊盘在与互连基底的底表面垂直的方向上不与下焊盘对齐。
2.根据权利要求1所述的半导体封装件，所述半导体封装件还包括位于半导体芯片和金属层之间的粘合层，
其中，粘合层包括热固性聚合物或热塑性聚合物。
3.根据权利要求1所述的半导体封装件，其中，再分布基底包括绝缘图案和位于绝缘图案之间的导电图案，
其中，金属层和导电图案具有比半导体芯片的热膨胀系数大的热膨胀系数。
4.根据权利要求1所述的半导体封装件，其中，金属层具有比半导体芯片的热导率大的热导率。
5.根据权利要求1所述的半导体封装件，所述半导体封装件还包括位于互连基底和金属层上的上封装件，
其中，上封装件电连接到导电构件。
6.一种半导体封装件，所述半导体封装件包括：
基底；
半导体芯片，位于基底上；
第一金属层，位于半导体芯片上；
互连基底，与半导体芯片并排设置在基底上，并且在平面图中围绕半导体芯片；以及
模制层，位于半导体芯片和互连基底之间的间隙中，
其中，互连基底包括基础层和延伸穿过基础层的导电构件，
其中，导电构件包括：下焊盘，位于互连基底的底表面上；线图案，位于基础层之间；过孔，穿透基础层；以及上焊盘，位于基础层的顶表面上，上焊盘通过过孔和线图案连接到下焊盘，并且
其中，上焊盘在与互连基底的底表面垂直的方向上不与下焊盘对齐。
7.根据权利要求6所述的半导体封装件，其中，
互连基底包括穿透其内部的孔，
半导体芯片设置在互连基底的孔中。
8.根据权利要求7所述的半导体封装件，其中，半导体芯片在所述孔中设置为多个。
9.根据权利要求6所述的半导体封装件，其中，下焊盘包括下接地焊盘和下信号焊盘，线图案包括接地线图案和信号线图案，过孔包括接地过孔和信号过孔，上焊盘包括上接地焊盘和上信号焊盘，
其中，下接地焊盘、接地线图案、接地过孔和上接地焊盘包括在接地图案中，下信号焊盘、信号线图案、信号过孔和上信号焊盘包括在信号图案中，
其中，第一金属层延伸到接地图案上并且连接到接地图案，
其中，第一金属层与信号图案绝缘。
10.根据权利要求9所述的半导体封装件，所述半导体封装件还包括设置在半导体芯片上并且与第一金属层分隔开的第二金属层，
其中，第二金属层延伸到信号图案上并且连接到信号图案，
其中，第二金属层与接地图案绝缘。
11.根据权利要求6所述的半导体封装件，所述半导体封装件还包括位于互连基底和半导体芯片上的中间层，
其中，第一金属层设置在中间层中。
12.根据权利要求11所述的半导体封装件，其中，中间层包括：
绝缘层，包括彼此面对的第一表面和第二表面，其中，第一金属层设置在绝缘层的第一表面上；
金属图案，位于绝缘层的第一表面上；以及
金属过孔，设置在绝缘层中，并且分别设置在第一金属层和金属图案上。
13.根据权利要求11所述的半导体封装件，其中，中间层包括：
绝缘层，包括彼此面对的第一表面和第二表面，其中，第一金属层设置在绝缘层的第一表面上；
金属图案，位于绝缘层的第二表面上；以及
金属过孔，穿透绝缘层，并且分别连接到第一金属层和金属图案。
14.根据权利要求6所述的半导体封装件，其中，互连基底在平面图中具有矩形形状，并且在基底上设置为多个。
15.一种半导体封装件，所述半导体封装件包括：
再分布基底；
互连基底，位于再分布基底上，互连基底包括穿透其内部的孔；
半导体芯片，位于再分布基底上且位于互连基底的孔中；
金属层，位于半导体芯片上；以及
模制层，位于半导体芯片和互连基底之间的间隙中，
其中，互连基底包括基础层和延伸穿过基础层的导电构件，
其中，互连基底的顶表面定位在与金属层的顶表面平齐或者比金属层的顶表面的水平高的水平，
其中，模制层覆盖互连基底的顶表面和金属层的顶表面，并且
其中，金属层具有与半导体芯片的宽度和平面形状基本相同的宽度和平面形状。
16.根据权利要求15所述的半导体封装件，所述半导体封装件还包括位于半导体芯片和金属层之间的粘合层，
其中，粘合层包括热固性聚合物或热塑性聚合物。
17.根据权利要求15所述的半导体封装件，其中，导电构件包括：
下焊盘，位于互连基底的底表面上；
线图案，位于基础层之间；
过孔，穿透基础层；以及
上焊盘，位于基础层的顶表面上，
其中，上焊盘通过过孔和线图案连接到下焊盘。
18.根据权利要求15所述的半导体封装件，其中，再分布基底包括绝缘图案和位于绝缘图案之间的导电图案，
其中，金属层和导电图案具有比半导体芯片的热膨胀系数大的热膨胀系数。
19.根据权利要求15所述的半导体封装件，其中，金属层具有比半导体芯片的热导率大的热导率。
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US10347611B2 (en) 2019-07-09
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