Nothing Special   »   [go: up one dir, main page]

Ko et al., 2018 - Google Patents

Single‐ended voltage‐mode duobinary transmitter with feedback time reduced parallel precoder

Ko et al., 2018

View PDF @Full View
Document ID
4670619261963573842
Author
Ko H
Chae J
Kim S
Publication year
Publication venue
Electronics Letters

External Links

Snippet

A duobinary transmitter (TX) is presented in a single‐ended topology using voltage‐mode drivers to support dynamic random access memory (DRAM) interface. A four‐phase parallel duobinary precoder is included. It relaxes one of the critical timing requirements of the …
Continue reading at ietresearch.onlinelibrary.wiley.com (PDF) (other versions)

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03343—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels; Baseband coding techniques specific to data transmission systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses

Similar Documents

Publication Publication Date Title
US7715474B2 (en) Decision feedback equalizer (DFE) architecture
Park et al. 30-Gb/s 1.11-pJ/bit single-ended PAM-3 transceiver for high-speed memory links
Han et al. Design techniques for a 60-Gb/s 288-mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65-nm CMOS technology
Min et al. A 20 Gb/s triple-mode (PAM-2, PAM-4, and duobinary) transmitter
Shah et al. Fractional order constant modulus blind algorithms with application to channel equalisation
Shi et al. Hardware‐efficient slope‐error algorithm based PAM4 baud rate CDR scheme for 40 Gb/s receiver
De Keulenaer et al. 84 Gbit/s SiGe BiCMOS duobinary serial data link including Serialiser/Deserialiser (SERDES) and 5‐tap FFE
Ko et al. Single‐ended voltage‐mode duobinary transmitter with feedback time reduced parallel precoder
Chiu et al. A 32Gb/s time-based PAM-4 transceiver for high-speed DRAM interfaces with in-situ channel loss and bit-error-rate monitors
EP3353967B1 (en) Pulsed decision feedback equalization circuit
Liu et al. High‐efficiency and noise‐robust DCSK approach based on an analytically solvable chaotic oscillator
Verbeke et al. Inverse Alexander phase detector
Beukema Design considerations for high-data-rate chip interconnect systems
Yoon et al. A 4.5 Gb/s/pin transceiver with hybrid inter‐symbol interference and far‐end crosstalk equalization for next‐generation high‐bandwidth memory interface
He et al. A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS
Chen et al. Pre‐emphasis transmitter (0.007 mm2, 8 Gbit/s, 0–14 dB) with improved data zero‐crossing accuracy in 65 nm CMOS
Rashdan Dual-time resolution time-based transceiver for low-power serial interfaces
Aguirre et al. 3.125 Gbit/s CMOS transceiver for duobinary modulation over 50‐m SI‐POF channels
Wang et al. Power‐efficient pre‐emphasis method for transmitters with LVDS drivers
Wu et al. Low complexity detection based on selective message passing for SCMA systems
Park et al. 12 Gbit/s three‐tap FFE half‐rate transmitter with low jitter clock buffering scheme
Min et al. 0.5–4.4 Gbit/s PAM4/NRZ dual‐mode transceiver with 0.6 V near‐ground NMOS driver for low‐power memory interface
Pola et al. A Low‐Complexity Decision Feedforward Equalizer Architecture for High‐Speed Receivers on Highly Dispersive Channels
Kossel et al. Feedback delay reduction of Tomlinson–Harashima precoder in 14 nm CMOS via pipelined MAC units operated entirely with CSA arithmetic
Wang et al. A 56 Gbps 4‐tap PAM‐4 direct decision feedback equaliser with negative capacitance employing dynamic CML comparators in 65‐nm CMOS