Nothing Special   »   [go: up one dir, main page]

Wang et al., 2021 - Google Patents

A 56 Gbps 4‐tap PAM‐4 direct decision feedback equaliser with negative capacitance employing dynamic CML comparators in 65‐nm CMOS

Wang et al., 2021

View PDF @Full View
Document ID
11684480458842086849
Author
Wang D
Zhao Z
Wang Z
Zhang C
Wang Z
Chen H
Publication year
Publication venue
Electronics Letters

External Links

Snippet

Here, a 4‐level pulse amplitude modulation direct decision feedback equaliser (DFE) with a novel dynamic current‐mode‐logic comparator (DCMLC) is presented. The DCMLC breaks the trade‐off between settling time and regeneration time in traditional CML comparator …
Continue reading at ietresearch.onlinelibrary.wiley.com (PDF) (other versions)

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L2025/03433Arrangements for removing intersymbol interference characterised by equaliser structure
    • H04L2025/03439Fixed structures
    • H04L2025/03445Time domain
    • H04L2025/03471Tapped delay lines
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L25/03012Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/08Modifications for reducing interference; Modifications for reducing effects due to line faults; Receiver end arrangements for detecting or overcoming line faults
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/06Dc level restoring means; Bias distortion correction decision circuits providing symbol by symbol detection
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION

Similar Documents

Publication Publication Date Title
Dickson et al. A 12-Gb/s 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology
Zheng et al. A 40-Gb/s quarter-rate SerDes transmitter and receiver chipset in 65-nm CMOS
Park et al. 30-Gb/s 1.11-pJ/bit single-ended PAM-3 transceiver for high-speed memory links
Lu et al. Design techniques for a 66 Gb/s 46 mW 3-tap decision feedback equalizer in 65 nm CMOS
Han et al. Design techniques for a 60-Gb/s 288-mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65-nm CMOS technology
Lee et al. Current-mode transceiver for silicon interposer channel
CN107005506B (en) Delay elastic decision feedback equalizer
Yi et al. A time-based receiver with 2-tap decision feedback equalizer for single-ended mobile DRAM interface
Chen et al. A 0.002-mm $^{2} $6.4-mW 10-Gb/s Full-Rate Direct DFE Receiver With 59.6% Horizontal Eye Opening Under 23.3-dB Channel Loss at Nyquist Frequency
Seo et al. A 7.8-Gb/s 2.9-pJ/b single-ended receiver with 20-tap DFE for highly reflective channels
Balachandran et al. 0.058 mm2 13 Gbit/s inductorless analogue equaliser with low‐frequency equalisation compensating 15 dB channel loss
Shi et al. Hardware‐efficient slope‐error algorithm based PAM4 baud rate CDR scheme for 40 Gb/s receiver
Chiu et al. A 32Gb/s time-based PAM-4 transceiver for high-speed DRAM interfaces with in-situ channel loss and bit-error-rate monitors
Wang et al. A 56 Gbps 4‐tap PAM‐4 direct decision feedback equaliser with negative capacitance employing dynamic CML comparators in 65‐nm CMOS
Cai et al. A 1.25–12.5 Gbps adaptive CTLE with asynchronous statistic eye‐opening monitor
Ding et al. A 112-Gb/s PAM-4 transmitter with a 2-tap fractional-spaced FFE in 65-nm CMOS
He et al. 40 Gbps 4‐level pulse amplitude modulation closed‐loop decision‐feedback equaliser with high‐speed comparator in 55 nm CMOS technology
Ko et al. Single‐ended voltage‐mode duobinary transmitter with feedback time reduced parallel precoder
Yuan et al. 10 Gbit/s serial link receiver with speculative decision feedback equaliser using mixed‐signal adaption in 65 nm CMOS technology
Lv et al. A 2-40 Gb/s PAM4/NRZ Dual-mode Wireline Transmitter with 4: 1 MUX in 65-nm CMOS
Chen et al. Pre‐emphasis transmitter (0.007 mm2, 8 Gbit/s, 0–14 dB) with improved data zero‐crossing accuracy in 65 nm CMOS
Sim et al. A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques
Yu et al. Hybrid optimisation method of sparse FIR DFEs based on reweighted ℓ1‐norm minimisation and greedy algorithms
Yoon et al. A 4.5 Gb/s/pin transceiver with hybrid inter‐symbol interference and far‐end crosstalk equalization for next‐generation high‐bandwidth memory interface
Na et al. A 20‐Gb/s 4‐tap time‐domain DFE with pulse width modulation for a DQ‐DQS matched parallel receiver