OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Deep learning toolkit-enabled VLSI placement

A High-performance Timing Analysis Tool for VLSI Systems

The PoC Library has been forked to github.com/VHDL/PoC. See new address below

The next generation of OpenLane, rewritten from scratch with a modular architecture

Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor

A modern and open-source cross-platform software for chips reverse engineering.

Open source software for chip reverse engineering.

Standard Cell Library based Memory Compiler using FF/Latch cells

Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization

A browser-based SPICE circuit simulator

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

A Reconfigurable RISC-V Core for Approximate Computing

ACT hardware description language and core tools.

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

Материалы для курсов по проектированию цифровых вычислительных систем

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

VLSI EDA Global Router

EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!