The PoC Library has been forked to github.com/VHDL/PoC. See new address below

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

cryptography ip-cores in vhdl / verilog

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

Library of reusable VHDL components

Repository to store all design and testbench files for Senior Design

This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol

Network protocol libraries for VHDL test benches

Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA

This repo contains golden vector and randomization testbenches for SRAM module.

This repository contains source code for labs and projects involving FPGA and Verilog based designs

Reusable HDL modules, packages, and testbench utilities for FPGA and ASIC development, supporting both VHDL and Verilog.

A "C pseudorandom generator" of VHDL testbenches for Digital Systems Design project at Politecnico di Milano.

A VHDL code base that contains Utility Packages for both HDL and Testbenches

My work for the laboratory exercises provided by intel FPGAcademy (Digital Logic) during my internship at PyramidTech in Summer 2022.

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and qsf files for pin assignments.

Verilog design and testbench files for Flip Flop, Counters, RAM, FIFO, Shift Registers and other sequential logic circuits

This repo contains the verification basics of System verilog and UVM