The next generation of OpenLane, rewritten from scratch with a modular architecture

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs

JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.

tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles

Gate-level visualization generator for SKY130-based chip designs.

This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130

This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral RTL of an 8-bit Priority Encoder, using SkyWater 130 nm PDK.

PLL configuration generator for the Caravel management core

Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah

This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.

CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.

This is part of EC383 - Mini Project in VLSI Design.

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

The Openlane core holds the central schema definitions, resolvers, endpoints, and other tooling associated with the openlane product suite

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry