research-article

High-Level Synthesis of Key-Obfuscated RTL IP with Design Lockout and Camouflaging

Authors:

Sheikh Ariful Islam,

Love Kumar Sah,

Srinivas KatkooriAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 26, Issue 1

Article No.: 6, Pages 1 - 35

https://doi.org/10.1145/3410337

Published: 22 October 2020 Publication History

Abstract

We propose three orthogonal techniques to secure Register-Transfer-Level (RTL) Intellectual Property (IP). In the first technique, the key-based RTL obfuscation scheme is proposed at an early design phase during High-Level Synthesis (HLS). Given a control-dataflow graph, we identify operations on non-critical paths and leverage synthesis information during and after HLS to insert obfuscation logic. In the second approach, we propose a robust design lockout mechanism for a key-obfuscated RTL IP when an incorrect key is applied more than the allowed number of attempts. We embed comparators on obfuscation logic output to check if the applied key is correct or not and a finite-state machine checker to enforce design lockout. Once locked out, only an authorized user (designer) can unlock the locked IP. In the third technique, we design four variants of the obfuscating module to camouflage the RTL design. We analyze the security properties of obfuscation, design lockout, and camouflaging. We demonstrate the feasibility on four datapath-intensive IPs and one crypto core for 32-, 64-, and 128-bit key lengths under three design corners (best, typical, and worst) with reasonable area, power, and delay overheads on both ASIC and FPGA platforms.

References

[1]

R. Kumar. 2011. Simply fabless! IEEE Solid-State Circuits Magazine 3, 4 (Fall 2011), 8--14.

[2]

G. McGraw. 2004. Software security. IEEE Security 8 Privacy 2, 2 (2004), 80--83.

Digital Library

[3]

Y. Alkabani and F. Koushanfar. 2007. Active hardware metering for intellectual property protection and security. In Proceedings of the USENIX Security Symposium. 291--306.

Digital Library

[4]

F. Koushanfar, I. Hong, and M. Potkonjak. 2005. Behavioral synthesis techniques for intellectual property protection. ACM Transactions on Design Automation of Electronic Systems 10, 3 (July 2005), 523--545.

Digital Library

[5]

A. E. Caldwell, Hyun-Jin Choi, A. B. Kahng, S. Mantik, M. Potkonjak, Gang Qu, and J. L. Wong. 2004. Effective iterative techniques for fingerprinting design IP. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, 2 (Feb. 2004), 208--215.

Digital Library

[6]

R. S. Chakraborty and S. Bhunia. 2008. Hardware protection and authentication through netlist level obfuscation. In Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD’08). 674--677.

[7]

R. S. Chakraborty and S. Bhunia. 2010. RTL hardware IP protection using key-based control and data flow obfuscation. In Proceedings of the 2010 23rd International Conference on VLSI Design (VLSID’10). 405--410.

Digital Library

[8]

R. S. Chakraborty and S. Bhunia. 2009. Security through obscurity: An approach for protecting Register Transfer Level hardware IP. In Proceedings of the 2009 IEEE International Workshop on Hardware-Oriented Security and Trust. 96--99.

Digital Library

[9]

L. Li and H. Zhou. 2013. Structural transformation for best-possible obfuscation of sequential circuits. In Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST’13). 55--60.

[10]

R. S. Chakraborty and S. Bhunia. 2009. HARPOON: An obfuscation-based SoC design methodology for hardware protection. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, 10 (Oct. 2009), 1493--1502.

Digital Library

[11]

S. A. Islam, L. K. Sah, and S. Katkoori. 2019. DLockout: A design lockout technique for key obfuscated RTL IP designs. In Proceedings of the 2019 IEEE International Symposium on Smart Electronic Systems (iSES’19) (Formerly iNiS). 17--20.

[12]

L. W. Chow, J. P. Baukus, B. J. Wang, and R. P. Cocchi. 2012. Camouflaging a standard cell based integrated circuit. Google Patents. US Patent 8,151,235.

[13]

C. Pilato, F. Regazzoni, R. Karri, and S. Garg. 2018. TAO: Techniques for algorithm-level obfuscation during high-level synthesis. In Proceedings of the 2018 55th Annual Design Automation Conference (DAC’18). 1--6.

[14]

J. A. Roy, F. Koushanfar, and I. L. Markov. 2008. EPIC: Ending piracy of integrated circuits. In Proceedings of the 2008 Design, Automation, and Test in Europe Conference and Exhibition (DATE’08). 1069--1074.

[15]

P. G. Paulin and J. P. Knight. 1989. Force-directed scheduling for the behavioral synthesis of ASICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 8, 6 (June 1989), 661--679.

Digital Library

[16]

J. Zhang. 2016. A practical logic obfuscation technique for hardware security. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, 3 (March 2016), 1193--1197.

Digital Library

[17]

X. Wang, X. Jia, Q. Zhou, Y. Cai, J. Yang, M. Gao, and G. Qu. 2016. Secure and low-overhead circuit obfuscation technique with multiplexers. In Proceedings of the 2016 International Great Lakes Symposium on VLSI (GLSVLSI’16). 133--136.

[18]

A. Sengupta and D. Roy. 2017. Protecting IP core during architectural synthesis using HLT-based obfuscation. Electronics Letters 53, 13 (2017), 849--851.

[19]

A. R. Desai, M. S. Hsiao, C. Wang, L. Nazhandali, and S. Hall. 2013. Interlocking obfuscation for anti-tamper hardware. In Proceedings of the 8th Annual Cyber Security and Information Intelligence Research Workshop (CSIIRW’13). ACM, New York, NY, Article 8, 4 pages.

[20]

M. C. Hansen, H. Yalcin, and J. P. Hayes. 1999. Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering. IEEE Design 8 Test of Computers 16, 3 (1999), 72--80.

[21]

F. Brglez, D. Bryan, and K. Kozminski. 1989. Combinational profiles of sequential benchmark circuits. In Proceedings of the IEEE International Symposium on Circuits and Systems. IEEE, Los Alamitos, CA, 1929--1934.

[22]

Y. Lao and K. K. Parhi. 2015. Obfuscating DSP circuits via high-level transformations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, 5 (May 2015), 819--830.

Digital Library

[23]

A. Sengupta, D. Kachave, and D. Roy. 2019. Low cost functional obfuscation of reusable IP cores used in CE hardware through robust locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, 4 (April 2019), 604--616.

[24]

A. Sengupta, D. Roy, S. P. Mohanty, and P. Corcoran. 2017. DSP design protection in CE through algorithmic transformation based structural obfuscation. IEEE Transactions on Consumer Electronics 63, 4 (Nov. 2017), 467--476.

[25]

A. Sengupta, S. P. Mohanty, F. Pescador, and P. Corcoran. 2018. Multi-phase obfuscation of fault secured DSP designs with enhanced security feature. IEEE Transactions on Consumer Electronics 64, 3 (Aug. 2018), 356--364.

Digital Library

[26]

C. Pilato, K. Wu, S. Garg, R. Karri, and F. Regazzoni. 2019. TaintHLS: High-level synthesis for dynamic information flow tracking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, 5 (May 2019), 798--808.

[27]

S. A. Islam and S. Katkoori. 2018. High-level synthesis of key based obfuscated RTL datapaths. In Proceedings of the 2018 19th International Symposium on Quality Electronic Design (ISQED’18). 407--412.

[28]

Z. Jiang, S. Dai, G. E. Suh, and Z. Zhang. 2018. High-level synthesis with timing-sensitive information flow enforcement. In Proceedings of the 2018 International Conference on Computer-Aided Design (ICCAD’18). ACM, New York, NY, Article 88, 8 pages.

[29]

J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri. 2012. Logic encryption: A fault analysis perspective. In Proceedings of the 2012 Design, Automation, and Test in Europe Conference and Exhibition (DATE’12). 953--958.

[30]

R. Karmakar, N. Prasad, S. Chattopadhyay, R. Kapur, and I. Sengupta. 2017. A new logic encryption strategy ensuring key interdependency. In Proceedings of the 2017 30th International Conference on VLSI Design and the 2017 16th International Conference on Embedded Systems (VLSID’17). 429--434.

[31]

B. Colombier, L. Bossuet, and D. Hely. 2015. Reversible denial-of-service by locking gates insertion for IP cores design protection. In Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI. 210--215.

[32]

K. Shamsi, M. Li, T. Meade, Z. Zhao, D. Z. Pan, and Y. Jin. 2017. AppSAT: Approximately deobfuscating integrated circuits. In Proceedings of the 2017 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST’17). 95--100.

[33]

H. Zhou, R. Jiang, and S. Kong. 2017. CycSAT: SAT-based attack on cyclic logic encryptions. In Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD’17). 49--56.

[34]

Y. Shen and H. Zhou. 2017. Double DIP: Re-evaluating security of logic encryption algorithms. In Proceedings of the 2017 Great Lakes Symposium on VLSI (GLSVLSI’17). ACM, New York, NY, 179--184.

[35]

M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran. 2017. Security analysis of anti-SAT. In Proceedings of the 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC’17). 342--347.

[36]

K. Campbell, W. Zuo, and D. Chen. 2017. New advances of high-level synthesis for efficient and reliable hardware design. Integration 58 (2017), 189--214.

[37]

A. Mathur, M. Fujita, E. Clarke, and P. Urard. 2009. Functional equivalence verification tools in high-level synthesis flows. IEEE Design 8 Test of Computers 26, 4 (2009), 88--95.

[38]

P. Subramanyan, S. Ray, and S. Malik. 2015. Evaluating the security of logic encryption algorithms. In Proceedings of the 2015 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST’15). 137--143.

[39]

J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri. 2012. Security analysis of logic obfuscation. In Proceedings of the 2012 Design Automation Conference (DAC’12). 83--89.

[40]

T. Meade, S. Zhang, and Y. Jin. 2016. Netlist reverse engineering for high-level functionality reconstruction. In Proceedings of the 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC’16). 655--660.

Digital Library

[41]

P. Subramanyan, N. Tsiskaridze, W. Li, A. Gascon, W. Y. Tan, A. Tiwari, N. Shankar, S. A. Seshia, and S. Malik. 2014. Reverse engineering digital circuits using structural and functional analyses. IEEE Transactions on Emerging Topics in Computing 2, 1 (March 2014), 63--80.

[42]

Synopsys PDK. 2020. Teaching Resources. Retrieved September 26, 2020 from https://www.synopsys.com/community/university-program/teaching-resources.html.

[43]

A. Orailoglu and R. Karri. 1996. Automatic synthesis of self-recovering VLSI systems. IEEE Transactions on Computers 45, 2 (Feb. 1996), 131--142.

Digital Library

[44]

J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri. 2013. Security analysis of integrated circuit camouflaging. In Proceedings of the 2013 ACM SIGSAC Conference on Computer and Communications Security (CCS’13). ACM, New York, NY, 709--720.

[45]

G. D. Crescenzo, J. Rajendran, R. Karri, and N. Memon. 2017. Boolean circuit camouflage: Cryptographic models, limitations, provable results and a random oracle realization. In Proceedings of the 2017 Workshop on Attacks and Solutions in Hardware Security (ASHES’17). ACM, New York, NY, 7--16.

[46]

M. E. Massad, S. Garg, and M. V. Tripunitara. 2015. Integrated circuit (IC) decamouflaging: Reverse engineering camouflaged ICs within minutes. In Proceedings of the 2015 Network and Distributed System Security Symposium (NDSS’15). 1--14.

[47]

D. Liu, C. Yu, X. Zhang, and D. Holcomb. 2016. Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuits. In Proceedings of the 2016 Design, Automation, and Test in Europe Conference and Exhibition (DATE’16). 433--438.

[48]

M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran. 2020. Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing 8, 2 (2020), 517--532.

[49]

T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein. 2009. Introduction to Algorithms. MIT Press, Cambridge, MA.

[50]

S. M. Plaza and I. L. Markov. 2015. Solving the third-shift problem in IC piracy with test-aware logic locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, 6 (June 2015), 961--971.

Digital Library

[51]

J. Rajendran, O. Sinanoglu, and R. Karri. 2014. Regaining trust in VLSI design: Design-for-trust techniques. Proceedings of the IEEE 102, 8 (2014), 1266--1282.

[52]

C. Collberg and C. Thomborson. 2002. Watermarking, tamper-proofing, and obfuscation-tools for software protection. IEEE Transactions on Software Engineering 28, 8 (2002), 735--746.

Digital Library

[53]

R. Hourani, R. Jenkal, W. R. Davis, and W. Alexander. 2009. Automated design space exploration for DSP applications. Journal of Signal Processing Systems 56, 2 (Sept. 2009), 199--216.

Digital Library

[54]

S. Kobayashi, K. Mita, Y. Takeuchi, and M. Imai. 2002. Design space exploration for DSP applications using the ASIP development system PEAS-III. In Proceedings of the 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing, Vol. 3. 3168--3171.

[55]

A. C. J. Kienhuis. 1999. Design space exploration of stream-based dataflow architectures. Tijdschrift van het Nederlands Elektronika en Radiogenootschap 64, 5 (1999), 191--191.

[56]

R. Dutta, J. Roy, and R. Vemuri. 1992. Distributed design-space exploration for high-level synthesis systems. In Proceedings of the 1992 29th ACM/IEEE Design Automation Conference. 644--650.

[57]

P. Kocher, J. Jaffe, B. Jun, and P. Rohatgi. 2011. Introduction to differential power analysis. Journal of Cryptographic Engineering 1, 1 (April 2011), 5--27.

[58]

W. Yu and S. Kose. 2016. A voltage regulator-assisted lightweight AES implementation against DPA attacks. IEEE Transactions on Circuits and Systems I: Regular Papers 63, 8 (Aug. 2016), 1152--1163.

[59]

W. Fornaciari, P. Gubian, D. Sciuto, and C. Silvano. 1997. High-level power estimation of VLSI systems. In Proceedings of the 1997 IEEE International Symposium on Circuits and Systems (ISCAS’97), Vol. 3. 1804--1807.

[60]

S. Mangard. 2004. Hardware countermeasures against DPA—A statistical analysis of their effectiveness. In Proceedings of the Cryptographer’s Track at the RSA Conference (CT-RSA’04).

[61]

F.-X. Standaert, E. Peeters, G. Rouvroy, and J.-J. Quisquater. 2006. An overview of power analysis attacks against field programmable gate arrays. Proceedings of the IEEE 94, 2 (Feb. 2006), 383--394.

[62]

F. Standaert, G. Rouvroy, J.-J. Quisquater, and J.-D. Legat. 2003. A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL. In Proceedings of the 2003 ACM/SIGDA 11th International Symposium on Field Programmable Gate Arrays. ACM, New York, NY, 216--224.

Digital Library

[63]

M. Yasin, J. J. Rajendran, O. Sinanoglu, and R. Karri. 2016. On improving the security of logic locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, 9 (Sept. 2016), 1411--1424.

Digital Library

[64]

M. Finke. 2015. Equisatisfiable SAT Encodings of Arithmetical Operations. Retrieved September 26, 2020 from http://www.martin-finke.de/documents/Masterarbeit_bitblast_Finke.pdf.

[65]

C. Gopalakrishnan and S. Katkoori. 2002. Behavioral synthesis of datapaths with low leakage power. In Proceedings of the 2002 IEEE International Symposium on Circuits and Systems. Proceedings, Vol. 4. iv.

[66]

N. Dutt and C. Ramachandran. 1992. Benchmarks for the 1992 High Level Synthesis Workshop. Department of Information and Computer Science, University of California.

[67]

OpenCores. 2020. Home Page. Retrieved September 26, 2020 from https://opencores.org/.

[68]

G. L. Zhang, B. Li, B. Yu, D. Z. Pan, and U. Schlichtmann. 2018. TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing. In Proceedings of the 2018 Design, Automation, and Test in Europe Conference and Exhibition (DATE’18). 91--96.

[69]

M. Li, K. Shamsi, Y. Jin, and D. Z. Pan. 2018. TimingSAT: Decamouflaging timing-based logic obfuscation. In Proceedings of the 2018 IEEE International Test Conference (ITC’18). 1--10.

[70]

Express. n.d. Benchmarks. Retrieved September 26, 2020 from https://www.ece.ucsb.edu/EXPRESS/benchmark/.

[71]

M. Martins, J. M. Matos, R. P. Ribas, A. Reis, G. Schlinker, L. Rech, and J. Michelsen. 2015. Open cell library in 15nm FreePDK technology. In Proceedings of the 2015 International Symposium on Physical Design (ISPD’15). ACM, New York, NY, 171--178.

[72]

D. Kim and K. Choi. 1997. Power-conscious high level synthesis using loop folding. In Proceedings of the 34th Design Automation Conference. 441--445.

Cited By

Sharma SRoy DPawar D(2024)PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/370103230:1(1-34)Online publication date: 17-Oct-2024
https://dl.acm.org/doi/10.1145/3701032
Halder DLiu YAmberiadis KSrivastava ARay S(2024)PoTeNt: Post-Synthesis Obfuscation for Secure Network-on-Chip Architectures2024 IEEE 37th International System-on-Chip Conference (SOCC)10.1109/SOCC62300.2024.10737820(1-6)Online publication date: 16-Sep-2024
https://doi.org/10.1109/SOCC62300.2024.10737820
Sengupta AAnshul A(2024)A Survey of High-Level Synthesis-Based Hardware (IP) Watermarking ApproachesIEEE Design & Test10.1109/MDAT.2024.343505641:6(70-83)Online publication date: Dec-2024
https://doi.org/10.1109/MDAT.2024.3435056
Show More Cited By

Index Terms

High-Level Synthesis of Key-Obfuscated RTL IP with Design Lockout and Camouflaging
1. Security and privacy
  1. Security in hardware
    1. Hardware security implementation
      1. Hardware-based security protocols

Recommendations

Analyzing Security Vulnerabilities Induced by High-level Synthesis
High-level synthesis (HLS) is essential to map the high-level language (HLL) description (e.g., in C/C++) of hardware design to the corresponding Register Transfer Level (RTL) to produce hardware-independent design specifications with reduced design ...
Layout-driven RTL binding techniques for high-level synthesis
ISSS '96: Proceedings of the 9th international symposium on System synthesis

The importance of effective and efficient accounting of layout effects is well-established in high-level synthesis (HLS), since it allows more realistic exploration of the design space and the generation of solutions with predictable metrics. This ...
High-Level Synthesis: Past, Present, and Future

Editor's note:This article presents the history and evolution of HLS from research to industry adoption. The authors offer insights on why earlier attempts to gain industry adoption were not successful, why current HLS tools are finally seeing adoption, ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 26, Issue 1

January 2021

234 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3422280

Editor:
X. Sharon Hu
University of Notre Dame, USA

Issue’s Table of Contents

Copyright © 2020 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 22 October 2020

Accepted: 01 June 2020

Revised: 01 June 2020

Received: 01 January 2020

Published in TODAES Volume 26, Issue 1

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

18
Total Citations
View Citations
270
Total Downloads

Downloads (Last 12 months)47
Downloads (Last 6 weeks)4

Reflects downloads up to 30 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Sharma SRoy DPawar D(2024)PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/370103230:1(1-34)Online publication date: 17-Oct-2024
https://dl.acm.org/doi/10.1145/3701032
Halder DLiu YAmberiadis KSrivastava ARay S(2024)PoTeNt: Post-Synthesis Obfuscation for Secure Network-on-Chip Architectures2024 IEEE 37th International System-on-Chip Conference (SOCC)10.1109/SOCC62300.2024.10737820(1-6)Online publication date: 16-Sep-2024
https://doi.org/10.1109/SOCC62300.2024.10737820
Sengupta AAnshul A(2024)A Survey of High-Level Synthesis-Based Hardware (IP) Watermarking ApproachesIEEE Design & Test10.1109/MDAT.2024.343505641:6(70-83)Online publication date: Dec-2024
https://doi.org/10.1109/MDAT.2024.3435056
Sengupta ABhui NAnshul AChourasia V(2024)Bio-mimicking DNA fingerprint profiling for HLS watermarking to counter hardware IP piracyScientific Reports10.1038/s41598-024-73119-y14:1Online publication date: 28-Sep-2024
https://doi.org/10.1038/s41598-024-73119-y
Sengupta AAnshul A(2024)Hardware Security of Image Processing Cores Against IP Piracy Using PSO-Based HLS-Driven Multi-Stage Encryption Fused with Fingerprint SignatureSN Computer Science10.1007/s42979-024-03255-95:7Online publication date: 9-Oct-2024
https://doi.org/10.1007/s42979-024-03255-9
Yi HZhang JLiu S(2023)Optimizing RTL Code Obfuscation: New Methods Based on XML Syntax TreeApplied Sciences10.3390/app1401024314:1(243)Online publication date: 27-Dec-2023
https://doi.org/10.3390/app14010243
Aksoy LNguyen QAlmeida FRaik JFlottes MDupuis SPagliarini S(2023)Hybrid Protection of Digital FIR FiltersIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.325364131:6(812-825)Online publication date: 1-Jun-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3253641
Zuzak MLiu YSrivastava A(2023)Security-Aware Resource Binding to Enhance Logic ObfuscationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.329445342:12(4528-4540)Online publication date: Dec-2023
https://doi.org/10.1109/TCAD.2023.3294453
Anshul ASengupta A(2023)A Survey of High Level Synthesis Based Hardware Security Approaches for Reusable IP Cores [Feature]IEEE Circuits and Systems Magazine10.1109/MCAS.2023.332560723:4(44-62)Online publication date: Dec-2024
https://doi.org/10.1109/MCAS.2023.3325607
Rathor MSengupta A(2023)Revisiting Black-Hat HLS: A Lightweight Countermeasure to HLS-Aided Trojan AttackIEEE Embedded Systems Letters10.1109/LES.2023.332779316:2(170-173)Online publication date: 26-Oct-2023
https://dl.acm.org/doi/10.1109/LES.2023.3327793
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

HTML Format

View this article in HTML Format.

Media

Figures

Other

Tables

View Issue’s Table of Contents