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High-Level Synthesis: Past, Present, and Future

Published: 01 July 2009 Publication History

Abstract

Editor's note:This article presents the history and evolution of HLS from research to industry adoption. The authors offer insights on why earlier attempts to gain industry adoption were not successful, why current HLS tools are finally seeing adoption, and what to expect as HLS evolves toward system-level design.—Andres Takach, Mentor Graphics

Cited By

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  • (2024)A Testing Program and Pragma Combination Selection Based Framework for High-Level Synthesis Tool Pragma-Related Bug DetectionIEEE Transactions on Software Engineering10.1109/TSE.2024.336855350:4(937-955)Online publication date: 22-Feb-2024
  • (2023)FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific CompilerACM Transactions on Architecture and Code Optimization10.1145/362952320:4(1-25)Online publication date: 25-Oct-2023
  • (2023)HDLRuby: A Ruby Extension for Hardware Description and its Translation to Synthesizable Verilog HDLACM Transactions on Embedded Computing Systems10.1145/3581757Online publication date: 1-Feb-2023
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Information & Contributors

Information

Published In

cover image IEEE Design & Test
IEEE Design & Test  Volume 26, Issue 4
July 2009
102 pages

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 July 2009

Author Tags

  1. ESL synthesis
  2. High-level synthesis
  3. behavioral synthesis
  4. commercial use
  5. design and test
  6. history

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Cited By

View all
  • (2024)A Testing Program and Pragma Combination Selection Based Framework for High-Level Synthesis Tool Pragma-Related Bug DetectionIEEE Transactions on Software Engineering10.1109/TSE.2024.336855350:4(937-955)Online publication date: 22-Feb-2024
  • (2023)FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific CompilerACM Transactions on Architecture and Code Optimization10.1145/362952320:4(1-25)Online publication date: 25-Oct-2023
  • (2023)HDLRuby: A Ruby Extension for Hardware Description and its Translation to Synthesizable Verilog HDLACM Transactions on Embedded Computing Systems10.1145/3581757Online publication date: 1-Feb-2023
  • (2023)On the RTL Implementation of FINN Matrix Vector UnitACM Transactions on Embedded Computing Systems10.1145/354714122:6(1-27)Online publication date: 9-Nov-2023
  • (2023)The Good, the Bad and the Ugly: Practices and Perspectives on Hardware Acceleration for Embedded Image ProcessingJournal of Signal Processing Systems10.1007/s11265-023-01885-595:10(1181-1201)Online publication date: 1-Oct-2023
  • (2023)Achieving high coverage in hardware equivalence checking via concolic verificationFormal Methods in System Design10.1007/s10703-023-00414-160:3(329-349)Online publication date: 7-Mar-2023
  • (2023)FPGA-Based Hardware/Software Codesign for Video Encoder on IoT Edge PlatformsComputational Science and Its Applications – ICCSA 2023 Workshops10.1007/978-3-031-37117-2_7(82-96)Online publication date: 3-Jul-2023
  • (2022)Pushing the Level of Abstraction of Digital System Design: A Survey on How to Program FPGAsACM Computing Surveys10.1145/353298955:5(1-48)Online publication date: 3-Dec-2022
  • (2022)A Case for Precise, Fine-Grained Pointer Synthesis in High-Level SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/349143027:4(1-26)Online publication date: 8-Mar-2022
  • (2022)High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media ApplicationsACM Transactions on Design Automation of Electronic Systems10.1145/349121527:4(1-34)Online publication date: 8-Mar-2022
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