research-article

Automatic Synthesis of Self-Recovering VLSI Systems

Authors:

Alex Orailoglu,

Ramesh KarriAuthors Info & Claims

IEEE Transactions on Computers, Volume 45, Issue 2

Pages 131 - 142

https://doi.org/10.1109/12.485368

Published: 01 February 1996 Publication History

Abstract

In this paper, we will describe an integrated system for synthesizing self-recovering microarchitectures called ${\cal SYNCERE}$. In the ${\cal SYNCERE}$model for self-recovery, transient faults are detected using duplication and comparison, while recovery from transient faults is accomplished via checkpointing and rollback. ${\cal SYNCERE}$initially inserts checkpoints subject to designer specified recovery time constraints. Subsequently, ${\cal SYNCERE}$incorporates detection constraints by ensuring that two copies of the computation are executed on disjoint hardware. Towards ameliorating the dedicated hardware required for the original and duplicate computations, ${\cal SYNCERE}$imposes intercopy hardware disjointness at a sub-computation level instead of at the overall computation level. The overhead is further moderated by restructuring the pliable input representation of the computation. ${\cal SYNCERE}$has successfully derived numerous self-recovering microarchitectures. Towards validating the methodology for designing fault-tolerant VLSI ICs, we carried out a physical design of a self-recovering 16-point FIR filter.

References

[1]

P. Ames P. Miles E. Milham C. Pilch W. Rodda L. Tedesco and B.V. Tine, "Automotive electronics: A design and test roundtable," IEEE Design and Test of Computers, vol. 35, pp. 84-93, 1992.

[2]

P. Banerjee and J.A. Abraham, "Fault-secure algorithms for multiple processor systems," Proc. 11th Int'l Symp. Computer Architecture, pp. 279-287, 1984.

Digital Library

[3]

D. Blough and A. Nicolau, "Fault tolerance in super-scalar and VLSI processors," Proc. 1992 IEEE Workshop Fault-Tolerant Parallel and Distributed Systems, pp. 193-200, 1992.

[4]

H.H. Braess, "Electronics—The co-evolution of intelligence in automobiles and road traffic," Proc. Sixth Int'l Conf. Automotive Electronics, pp. 109, 1987.

[5]

A. Casotto, OCTTOOLS 5.1: The User Guide. Electronics Research Laboratory, Univ. of California, Berkeley, 1991.

[6]

X. Castillo S.R. McConnell and D.P. Siewiorek, "Derivation and calibration of a transient errore reliability model," IEEE Trans. Computers, vol. 31, no. 7, pp. 658-671, July 1982.

[7]

K.M. Chandy and C.V. Ramamoorthy, "Rollback and recovery strategies for computer programs," IEEE Trans. Computers, vol. 37, pp. 546-556, 1972.

Digital Library

[8]

A. Dahbura K. Sabnani and W. Hery, "Spare capacity as a means for fault detection and diagnosis," IEEE Trans. Computers, vol. 38, no. 6, pp. 881-891, June 1989.

Digital Library

[9]

D.D. Gajski N.D. Dutt A. Wu and S. Lin, High-Level Synthesis: Introduction to Chip and System Design. Kluwer, 1992.

Digital Library

[10]

C.H. Golub and C. van Loan, Matrix Computation. Baltimore: Johns Hopkins Univ. Press, 1989.

Digital Library

[11]

D. Gu D.J. Rosenkrantz and S.S. Ravi, "Construction and analysis of fault-secure multiprocessor schedules," Proc. 21st Int'l Symp. Fault-Tolerant Computing, pp. 120-127, 1991.

[12]

L.M. Guerra M.M. Potkonjak and J.M. Rabaey, "High level synthesis for reconfigurable datapath structures," Proc. 1993 IEEE Int'l Conf. Computer Aided Design, pp. 26-29, 1993.

Digital Library

[13]

I.G. Harris and A. Orailoglu, "Microarchitectural synthesis of VLSI designs with high test concurrency," Proc. 1994 Design Automation Conf., pp. 206-211, 1994.

Digital Library

[14]

B.W. Johnson, Design and Analysis of Fault-Tolerant Digital Systems. Addison-Wesley, 1989.

Digital Library

[15]

R. Karri K. Högstedt and A. Orailoglu, "Rapid prototyping of fault tolerant VLSI systems," Proc. Seventh Int'l Symp. High Level Synthesis, pp. 126-131, May 1994.

Digital Library

[16]

P.K. Lala, Fault-Tolerant and Fault-Testable Hardware Design. Prentice Hall Int'l, 1985.

Digital Library

[17]

R. Leveugle and G. Saucier, "Optimized synthesis of concurrently checked controllers," IEEE Trans. Computers, vol. 39, no. 4, pp. 419-425, Apr. 1990.

Digital Library

[18]

C.C. Li and W.K. Fuchs, "CATCH: Compiler assisted techniques for checkpointing," Proc. 20th Int'l Symp. Fault-Tolerant Computing, pp. 74-81, 1990.

[19]

A. Orailoglu and R. Karri, "Coactive scheduling and checkpoint determination during high level synthesis of self recovering microarchitectures," IEEE Trans. VLSI Systems, vol. 2, no. 3, pp. 304-311, 1994.

Digital Library

[20]

A. Orailoglu and R. Karri, "Synthesis of fault-tolerant and real time microarchitectures," J. Systems and Software, vol. 25, no. 1, pp. 73-84, 1994.

Digital Library

[21]

A.C. Parker J.T. Pizarro and A. Mlinar, "MAHA: A program for datapath synthesis," Proc. 23rd Design Automation Conf., pp. 461-466, 1986.

Digital Library

[22]

P.G. Paulin and J.P. Knight, "Force-directed scheduling for the behavioral synthesis of ASICs," IEEE Trans. Computer-Aided Design, vol. 8, no. 6, pp. 661-679, 1989.

Digital Library

[23]

M. Peercy and P. Banerjee, "Fault tolerant VLSI systems," Proc. IEEE, vol. 81, no. 5, pp. 745-758, May 1993.

[24]

A.M. Saleh and J.H. Patel, "Transient-fault analysis for retry techniques," IEEE Trans. Reliability, vol. 37, no. 3, pp. 323-330, 1988.

[25]

R.M. Sedmak and H.L. Liebergot, "Fault tolerance of a general purpose computer implemented by very large scale integration," IEEE Trans. Computers, vol. 29, no. 6, pp. 492-500, June 1980.

Digital Library

[26]

R.J. Straub, "Automotive electronics IC reliability," Proc. Custom Integrated Circuits Conf., pp. 19.2.1-19.2.4, May 1990.

[27]

Y. Tamir M. Liang T. Lai and M. Tremblay, "The UCLA mirror processor: A building block for self-checking self-repairing computing nodes," Proc. 21st Int'l Symp. Fault Tolerant Computing, pp. 178-185, 1991.

[28]

Y. Tamir and M. Tremblay, "High-performance fault-tolerant VLSI systems using micro-rollback,". IEEE Trans. Computers, vol. 39, no. 4, pp. 548-554, Apr. 1990.

Digital Library

[29]

S. Toueg and Ö. Babaoglu, "On the optimum checkpoint selection problem," SIAM J. Computing, vol. 13, pp. 630-649, 1984.

Digital Library

[30]

M.M. Taso, "The design of C.fast: A single chip fault tolerant microprocessor," Proc. 12th Int'l Symp. Fault Tolerant Computing, pp. 63-69, 1982.

[31]

J.S. Upadhyaya and K.K. Saluja, "Rollback and recovery strategies for computer programs," IEEE Trans. Software Engineering, vol. 12, pp. 546-556, 1986.

[32]

R.A. Walker and D.E. Thomas, "Behavioral transformation for algorithmic level IC design," IEEE Trans. Computer-Aided Design, vol. 8, no. 10, pp. 1,115-1,128, 1989.

Digital Library

[33]

M.M. Yen W.K. Fuchs and J.A. Abraham, "Designing for concurrent error detection in VLSI: Application to a microprogram control unit," IEEE J. Solid State Circuits, vol. 22, no. 4, pp. 595-605, 1987.

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Automatic Synthesis of Self-Recovering VLSI Systems

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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 45, Issue 2

February 1996

127 pages

ISSN:0018-9340

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Copyright © Copyright © 1996 IEEE. All Rights Reserved.

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IEEE Computer Society

United States

Publication History

Published: 01 February 1996

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Cited By

Islam SSah LKatkoori S(2020)High-Level Synthesis of Key-Obfuscated RTL IP with Design Lockout and CamouflagingACM Transactions on Design Automation of Electronic Systems10.1145/341033726:1(1-35)Online publication date: 22-Oct-2020
https://dl.acm.org/doi/10.1145/3410337
Zhu ZTaher FCarrion Schafer BHomayoun HTaskin BMohsenin TZhao W(2019)Exploring Design Trade-offs in Fault-Tolerant Behavioral Hardware AcceleratorsProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3318020(291-294)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3318020
Wilson DShastri AStitt G(2017)A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault ToleranceInternational Journal of Reconfigurable Computing10.1155/2017/54197672017Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1155/2017/5419767
Karimi NMirkhani SNavabi ZLombardi FZhou HMacii EYan ZMassoud Y(2007)RT level reliability enhancement by constructing dynamic TMRSProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228829(172-175)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228829
Saha G(2006)Software based fault toleranceUbiquity10.1145/1149633.11479952006:July(1-1)Online publication date: 1-Jul-2006
https://dl.acm.org/doi/10.1145/1149633.1147995
Oikonomakos PZwolinski M(2006)On the Design of Self-Checking Controllers with Datapath InteractionsIEEE Transactions on Computers10.1109/TC.2006.18555:11(1423-1434)Online publication date: 1-Nov-2006
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Jiang J(2005)An error recoverable structure based on complementary logic and alternating-retryJournal of Computer Science and Technology10.1007/s11390-005-0885-420:6(885-894)Online publication date: 1-Nov-2005
https://dl.acm.org/doi/10.1007/s11390-005-0885-4
Oikonomakos PZwolinski MAl-Hashimi B(2003)Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability MetricProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022791Online publication date: 3-Mar-2003
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Antola AFerrandi FPiuri VSami M(2001)Semiconcurrent Error Detection in Data PathsIEEE Transactions on Computers10.1109/12.92615950:5(449-465)Online publication date: 1-May-2001
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Karri RKim KPotkonjak M(2000)Computer Aided Design of Fault-Tolerant Application Specific Programmable ProcessorsIEEE Transactions on Computers10.1109/12.89594249:11(1272-1284)Online publication date: 1-Nov-2000
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