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Layout-driven RTL binding techniques for high-level synthesis

Authors:

Min Xu,

F. J. KurdahiAuthors Info & Claims

ISSS '96: Proceedings of the 9th international symposium on System synthesis

Page 33

Published: 06 November 1996 Publication History

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Abstract

The importance of effective and efficient accounting of layout effects is well-established in high-level synthesis (HLS), since it allows more realistic exploration of the design space and the generation of solutions with predictable metrics. This feature is highly desirable in order to avoid unnecessary iterations through the design process. In this paper, we address the problem of layout-driven register-transfer-level (RTL) binding as this step has a direct relevance on the final performance of the design. By producing not only an RTL design but also an approximate physical topology of the chip level implementation, we ensure that the solution will perform at the predicted metric once implemented, thus avoiding unnecessary delays in the design process.

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Cited By

View all

Cong JFan YYang XZhang ZPedram MAlpert C(2003)Architecture and synthesis for multi-cycle communicationProceedings of the 2003 international symposium on Physical design10.1145/640000.640040(190-196)Online publication date: 6-Apr-2003
https://dl.acm.org/doi/10.1145/640000.640040
Zhu JGajski D(1999)Soft scheduling in high level synthesisProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.309917(219-224)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1145/309847.309917
Xu MKurdahi F(1997)RTL Synthesis with Physical and Controller InformationProceedings of the 1997 European conference on Design and Test10.5555/787260.787678Online publication date: 17-Mar-1997
https://dl.acm.org/doi/10.5555/787260.787678

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Published In

ISSS '96: Proceedings of the 9th international symposium on System synthesis

November 1996

146 pages

ISBN:0818675632

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IEEE Computer Society

United States

Publication History

Published: 06 November 1996

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9ISSS96

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SIGDA

9ISSS96: 9th International Symposium on Systems Synthesis

November 6 - 8, 1996

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Overall Acceptance Rate 38 of 71 submissions, 54%

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Cited By

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Cong JFan YYang XZhang ZPedram MAlpert C(2003)Architecture and synthesis for multi-cycle communicationProceedings of the 2003 international symposium on Physical design10.1145/640000.640040(190-196)Online publication date: 6-Apr-2003
https://dl.acm.org/doi/10.1145/640000.640040
Zhu JGajski D(1999)Soft scheduling in high level synthesisProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.309917(219-224)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1145/309847.309917
Xu MKurdahi F(1997)RTL Synthesis with Physical and Controller InformationProceedings of the 1997 European conference on Design and Test10.5555/787260.787678Online publication date: 17-Mar-1997
https://dl.acm.org/doi/10.5555/787260.787678

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An Introduction to High-Level Synthesis

High-Level Synthesis: Past, Present, and Future

A comprehensive estimation technique for high-level synthesis