research-article

High-Level Synthesis of Key-Obfuscated RTL IP with Design Lockout and Camouflaging

Authors:

Sheikh Ariful Islam,

Love Kumar Sah,

Srinivas KatkooriAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 26, Issue 1

Article No.: 6, Pages 1 - 35

https://doi.org/10.1145/3410337

Published: 22 October 2020 Publication History

Abstract

We propose three orthogonal techniques to secure Register-Transfer-Level (RTL) Intellectual Property (IP). In the first technique, the key-based RTL obfuscation scheme is proposed at an early design phase during High-Level Synthesis (HLS). Given a control-dataflow graph, we identify operations on non-critical paths and leverage synthesis information during and after HLS to insert obfuscation logic. In the second approach, we propose a robust design lockout mechanism for a key-obfuscated RTL IP when an incorrect key is applied more than the allowed number of attempts. We embed comparators on obfuscation logic output to check if the applied key is correct or not and a finite-state machine checker to enforce design lockout. Once locked out, only an authorized user (designer) can unlock the locked IP. In the third technique, we design four variants of the obfuscating module to camouflage the RTL design. We analyze the security properties of obfuscation, design lockout, and camouflaging. We demonstrate the feasibility on four datapath-intensive IPs and one crypto core for 32-, 64-, and 128-bit key lengths under three design corners (best, typical, and worst) with reasonable area, power, and delay overheads on both ASIC and FPGA platforms.

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Index Terms

High-Level Synthesis of Key-Obfuscated RTL IP with Design Lockout and Camouflaging
1. Security and privacy
  1. Security in hardware
    1. Hardware security implementation
      1. Hardware-based security protocols

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 26, Issue 1

January 2021

234 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3422280

Editor:
X. Sharon Hu
University of Notre Dame, USA

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Copyright © 2020 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 22 October 2020

Accepted: 01 June 2020

Revised: 01 June 2020

Received: 01 January 2020

Published in TODAES Volume 26, Issue 1

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Halder DLiu YAmberiadis KSrivastava ARay S(2024)PoTeNt: Post-Synthesis Obfuscation for Secure Network-on-Chip Architectures2024 IEEE 37th International System-on-Chip Conference (SOCC)10.1109/SOCC62300.2024.10737820(1-6)Online publication date: 16-Sep-2024
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Sengupta AAnshul A(2024)A Survey of High-Level Synthesis-Based Hardware (IP) Watermarking ApproachesIEEE Design & Test10.1109/MDAT.2024.343505641:6(70-83)Online publication date: Dec-2024
https://doi.org/10.1109/MDAT.2024.3435056
Sengupta ABhui NAnshul AChourasia V(2024)Bio-mimicking DNA fingerprint profiling for HLS watermarking to counter hardware IP piracyScientific Reports10.1038/s41598-024-73119-y14:1Online publication date: 28-Sep-2024
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Sengupta AAnshul A(2024)Hardware Security of Image Processing Cores Against IP Piracy Using PSO-Based HLS-Driven Multi-Stage Encryption Fused with Fingerprint SignatureSN Computer Science10.1007/s42979-024-03255-95:7Online publication date: 9-Oct-2024
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