research-article

UltraSparc I: A Four-Issue Processor Supporting Multimedia

Authors:

Marc Tremblay,

J. Michael O'ConnorAuthors Info & Claims

IEEE Micro, Volume 16, Issue 2

Pages 42 - 50

https://doi.org/10.1109/40.491461

Published: 01 April 1996 Publication History

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Abstract

UltraSPARC-I is a general-purpose processor implementing the SPARC V9 64-bit RISC architecture. In addition to supporting this Instruction Set Architecture (ISA), UltraSPARC-I includes over 30 new multimedia instructions (VIS - Visual Instruction Set) that provide the most common operations related to image processing, two- and three-dimensional graphics, video compression/decompression algorithms, etc.The simple in-order execution model implemented on UltraSPARC-I allows a balance between a high clock rate and a relatively wide (four-issue) machine. Microarchitecture features allowing the processor to sustain an execution of four instructions per cycle even in the presence of conditional branches and cache misses are described. The second part of the article focuses on the microarchitecture features that the software can leverage to achieve higher performance, including some of the multimedia features implemented on chip.

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Cited By

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Chaudhuri MAgrawal MGaur JSubramoney S(2017)Micro-Sector CacheACM Transactions on Architecture and Code Optimization10.1145/304668014:1(1-29)Online publication date: 21-Mar-2017
https://dl.acm.org/doi/10.1145/3046680
Boyer MTarjan DSkadron K(2010)FederationACM Transactions on Architecture and Code Optimization10.1145/1880043.18800467:4(1-38)Online publication date: 30-Dec-2010
https://dl.acm.org/doi/10.1145/1880043.1880046
Silc JUngerer TRobic B(2007)Dynamic branch prediction and control speculationInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2007.0132871:1(2-13)Online publication date: 1-Apr-2007
https://dl.acm.org/doi/10.1504/IJHPSA.2007.013287
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UltraSparc I: A Four-Issue Processor Supporting Multimedia
1. General and reference
  1. Cross-computing tools and techniques

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Published In

IEEE Micro Volume 16, Issue 2

April 1996

146 pages

ISSN:0272-1732

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 April 1996

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Chaudhuri MAgrawal MGaur JSubramoney S(2017)Micro-Sector CacheACM Transactions on Architecture and Code Optimization10.1145/304668014:1(1-29)Online publication date: 21-Mar-2017
https://dl.acm.org/doi/10.1145/3046680
Boyer MTarjan DSkadron K(2010)FederationACM Transactions on Architecture and Code Optimization10.1145/1880043.18800467:4(1-38)Online publication date: 30-Dec-2010
https://dl.acm.org/doi/10.1145/1880043.1880046
Silc JUngerer TRobic B(2007)Dynamic branch prediction and control speculationInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2007.0132871:1(2-13)Online publication date: 1-Apr-2007
https://dl.acm.org/doi/10.1504/IJHPSA.2007.013287
Qiu XDubois M(2005)Moving Address Translation Closer to Memory in Distributed Shared-Memory MultiprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2005.8416:7(612-623)Online publication date: 1-Jul-2005
https://dl.acm.org/doi/10.1109/TPDS.2005.84
Yi JLilja DHawkins D(2005)Improving Computer Architecture Simulation Methodology by Adding Statistical RigorIEEE Transactions on Computers10.1109/TC.2005.18454:11(1360-1373)Online publication date: 1-Nov-2005
https://dl.acm.org/doi/10.1109/TC.2005.184
Tabrizi NBagherzadeh NKamalizad ADu HVassiliadis SGaudiot JPiuri V(2004)MaRSProceedings of the 1st conference on Computing frontiers10.1145/977091.977141(343-349)Online publication date: 14-Apr-2004
https://dl.acm.org/doi/10.1145/977091.977141
Yi JLilja DHawkins D(2003)A Statistically Rigorous Approach for Improving Simulation MethodologyProceedings of the 9th International Symposium on High-Performance Computer Architecture10.5555/822080.822822Online publication date: 8-Feb-2003
https://dl.acm.org/doi/10.5555/822080.822822
Schulte MSwartzlander E(2000)A Family of Variable-Precision Interval Arithmetic ProcessorsIEEE Transactions on Computers10.1109/12.85953549:5(387-397)Online publication date: 1-May-2000
https://dl.acm.org/doi/10.1109/12.859535
Albonesi DRonen RFarrens MSpillinger I(1999)Selective cache waysProceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture10.5555/320080.320119(248-259)Online publication date: 16-Nov-1999
https://dl.acm.org/doi/10.5555/320080.320119
Rothman JSmith APapatheodorou TValero MPolychronopoulos CMuraoka YLabarta J(1999)The pool of subsectors cache designProceedings of the 13th international conference on Supercomputing10.1145/305138.305156(31-42)Online publication date: 20-Jun-1999
https://dl.acm.org/doi/10.1145/305138.305156
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The MIPS R10000 Superscalar Microprocessor

UltraSPARC: Compiling for Maximum Floating Point Performance

Support for speculative execution in high-performance processors

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